linux-kernel - Re: [PATCH V1] dt-bindings: mmc: sdhci-msm: Add CQE reg map

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAD=FV=XO=xd-BRaXrJ4-L2gaMX6=njV35CSnMV153-DLN8dwvA@mail.gmail.com>
Date:   Wed, 12 Feb 2020 15:21:10 -0800
From:   Doug Anderson <dianders@...gle.com>
To:     Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
Cc:     Ulf Hansson <ulf.hansson@...aro.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Asutosh Das <asutoshd@...eaurora.org>,
        Sahitya Tummala <stummala@...eaurora.org>,
        Sayali Lokhande <sayalil@...eaurora.org>, cang@...eaurora.org,
        Ram Prakash Gupta <rampraka@...eaurora.org>,
        Linux MMC List <linux-mmc@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>
Subject: Re: [PATCH V1] dt-bindings: mmc: sdhci-msm: Add CQE reg map

Hi,

On Wed, Feb 12, 2020 at 4:00 AM Veerabhadrarao Badiganti
<vbadigan@...eaurora.org> wrote:
>
>
> On 2/11/2020 10:12 PM, Doug Anderson wrote:
> > Hi,
> >
> > On Tue, Feb 11, 2020 at 7:29 AM Veerabhadrarao Badiganti
> > <vbadigan@...eaurora.org> wrote:
> >> CQE feature has been enabled on sdhci-msm. Add CQE reg map
> >> that needs to be supplied for supporting CQE feature.
> >>
> >> Change-Id: I788c4bd5b7cbca16bc1030a410cc5550ed7204e1
> >> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
> >> ---
> >>   Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 5 +++++
> >>   1 file changed, 5 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> >> index 7ee639b..eaa0998 100644
> >> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> >> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> >> @@ -27,6 +27,11 @@ Required properties:
> >>   - reg: Base address and length of the register in the following order:
> >>          - Host controller register map (required)
> >>          - SD Core register map (required for msm-v4 and below)
> >> +       - CQE register map (Optional, needed only for eMMC and msm-v4.2 above)
> > I did a quick search and it appears that SD cards implementing 6.0 of
> > the spec can also use CQE.  Is that correct?  If so, maybe remove the
> > part about "eMMC"?
> On qcom platforms, only SDHC instance meant for eMMC has the CQE support.
> So mentioned that its needed only for eMMC.

Ah, got it.  Maybe mention this in the bindings?  Like "Optional, CQE
is only implemented on controllers meant for eMMC and version v4.2 and
above"


> > Maybe also change "needed" to "useful" to make it clear that this
> > entry isn't actually required for all msm-v4.2 controllers?
> sure.
> >
> >> +- reg-names: When CQE register map is supplied, below reg-names are required
> >> +       - "hc_mem" for Host controller register map
> >> +       - "core_mem" for SD cpre regoster map
> > s/regoster/register

Oh, also s/cpre/core


> >> +       - "cqhci_mem" for CQE register map
> > I'm at least slightly confused.  You say that reg-names are there only
> > if CQE register map is supplied.  ...and that requires 4.2 and above.
> > ...but "core_mem" is only there on 4.0 and below.  So there should
> > never be a "core_mem" entry?
> core_mem is present till <v5.0
> cqhci_mem is present on >=v4.2
> Say, for version v4.2 both are present; .... and for v5.0 only cqhci_mem
> is present.
>
> Both hc reg-map and core reg-map are being accessed through index.
> So no need to list the reg names 'hc_mem' & 'core_mem' in general.
>
> But coming to cqhci reg-map we can't access it with fixed index, since
> its index varies between 1/2
> based on controller version.
>
> So we are accessing it through reg-names. Since reg-names has to be
> associated with corresponding
> reg maps, other two reg-names (hc_mem & core_mem) also need to br listed
> when cqhci_mem is listed.
>
> That is the reason, I mentioned it like these are needed only cqe reg
> map is supplied.
> If it is creating confusion, i will remove that statement.

Ah.  I think I got confused!  When I saw "msm-v4 and below" in the
description of "SD Core register map", I assumed that means that
"v4.2" didn't have it.  Maybe would be less confusing to change to:

- SD Core register map (required for controllers earlier than msm-v5)

Then I think what you have can be fine.



> > Trying to specify that sanely in free-form text seems like it's gonna
> > be hard and not worth it.  You should probably transition to yaml
> > first?
> >
> >
> > I will also note that Rob isn't a huge fan of "reg-names".  In a
> > different conversation I think you mentioned you had a reason for
> > having it.  I guess just be prepared to defend yourself against Rob if
> > you feel strongly about keeping reg-names.
> Sure. Its the same reason mentioned in above comment.

OK.  You've convinced me.  It's still up to Rob but it seems like you
have a good justification now that I understand it better..  ;-)

I think you could send out a v2 with the small wording changes and
maybe it would be landable, but you'd want to follow up rather soon
with the yaml conversion.


-Doug