linux-kernel - Re: [PATCH V1] dt-bindings: mmc: sdhci-msm: Add CQE reg map

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1e3f8fc3-dde9-5aaf-12a9-0eb0bc5ceb83@codeaurora.org>
Date:   Wed, 12 Feb 2020 17:30:00 +0530
From:   Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
To:     Doug Anderson <dianders@...gle.com>
Cc:     Ulf Hansson <ulf.hansson@...aro.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Asutosh Das <asutoshd@...eaurora.org>,
        Sahitya Tummala <stummala@...eaurora.org>,
        Sayali Lokhande <sayalil@...eaurora.org>, cang@...eaurora.org,
        Ram Prakash Gupta <rampraka@...eaurora.org>,
        Linux MMC List <linux-mmc@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>
Subject: Re: [PATCH V1] dt-bindings: mmc: sdhci-msm: Add CQE reg map


On 2/11/2020 10:12 PM, Doug Anderson wrote:
> Hi,
>
> On Tue, Feb 11, 2020 at 7:29 AM Veerabhadrarao Badiganti
> <vbadigan@...eaurora.org> wrote:
>> CQE feature has been enabled on sdhci-msm. Add CQE reg map
>> that needs to be supplied for supporting CQE feature.
>>
>> Change-Id: I788c4bd5b7cbca16bc1030a410cc5550ed7204e1
>> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
>> ---
>>   Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
>> index 7ee639b..eaa0998 100644
>> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
>> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
>> @@ -27,6 +27,11 @@ Required properties:
>>   - reg: Base address and length of the register in the following order:
>>          - Host controller register map (required)
>>          - SD Core register map (required for msm-v4 and below)
>> +       - CQE register map (Optional, needed only for eMMC and msm-v4.2 above)
> I did a quick search and it appears that SD cards implementing 6.0 of
> the spec can also use CQE.  Is that correct?  If so, maybe remove the
> part about "eMMC"?
On qcom platforms, only SDHC instance meant for eMMC has the CQE support.
So mentioned that its needed only for eMMC.
>
> Maybe also change "needed" to "useful" to make it clear that this
> entry isn't actually required for all msm-v4.2 controllers?
sure.
>
>> +- reg-names: When CQE register map is supplied, below reg-names are required
>> +       - "hc_mem" for Host controller register map
>> +       - "core_mem" for SD cpre regoster map
> s/regoster/register
>
>
>> +       - "cqhci_mem" for CQE register map
> I'm at least slightly confused.  You say that reg-names are there only
> if CQE register map is supplied.  ...and that requires 4.2 and above.
> ...but "core_mem" is only there on 4.0 and below.  So there should
> never be a "core_mem" entry?
core_mem is present till <v5.0
cqhci_mem is present on >=v4.2
Say, for version v4.2 both are present; .... and for v5.0 only cqhci_mem 
is present.

Both hc reg-map and core reg-map are being accessed through index.
So no need to list the reg names 'hc_mem' & 'core_mem' in general.

But coming to cqhci reg-map we can't access it with fixed index, since 
its index varies between 1/2
based on controller version.

So we are accessing it through reg-names. Since reg-names has to be 
associated with corresponding
reg maps, other two reg-names (hc_mem & core_mem) also need to br listed 
when cqhci_mem is listed.

That is the reason, I mentioned it like these are needed only cqe reg 
map is supplied.
If it is creating confusion, i will remove that statement.
> Trying to specify that sanely in free-form text seems like it's gonna
> be hard and not worth it.  You should probably transition to yaml
> first?
>
>
> I will also note that Rob isn't a huge fan of "reg-names".  In a
> different conversation I think you mentioned you had a reason for
> having it.  I guess just be prepared to defend yourself against Rob if
> you feel strongly about keeping reg-names.
Sure. Its the same reason mentioned in above comment.
>
> -Doug