linux-kernel - Re: [PATCH v4 5/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP.

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Message-Id: <1581705458.3.2@crapouillou.net>
Date:   Fri, 14 Feb 2020 15:37:38 -0300
From:   Paul Cercueil <paul@...pouillou.net>
To:     周琰杰 "(Zhou Yanjie)" 
        <zhouyanjie@...yeetech.com>
Cc:     linux-mips@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        mark.rutland@....com, ralf@...ux-mips.org, paulburton@...nel.org,
        jiaxun.yang@...goat.com, chenhc@...ote.com, allison@...utok.net,
        tglx@...utronix.de, daniel.lezcano@...aro.org,
        geert+renesas@...der.be, krzk@...nel.org, keescook@...omium.org,
        ebiederm@...ssion.com, miquel.raynal@...tlin.com,
        paul@...die.org.uk, hns@...delico.com, sernia.zhou@...mail.com,
        zhenwenjin@...il.com, mips-creator-ci20-dev@...glegroups.com,
        1326991897@...com
Subject: Re: [PATCH v4 5/6] MIPS: CI20: Modify DTS to support high resolution
 timer for SMP.

Hi Zhou,

I think you can move this patch before the clocksource one - it will 
work with the old clocksource code and in generally it's a good idea to 
ensure (if possible) that you can git-bisect without ending up with a 
broken kernel.

-Paul


Le sam., févr. 15, 2020 at 02:02, 周琰杰 (Zhou Yanjie) 
<zhouyanjie@...yeetech.com> a écrit :
> Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for
> per core local timer, #2 for clocksource.
> 
> Tested-by: H. Nikolaus Schaller <hns@...delico.com>
> Tested-by: Paul Boddie <paul@...die.org.uk>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
> ---
> 
> Notes:
>     v1->v2:
>     No change.
> 
>     v2->v3:
>     No change.
> 
>     v3->v4:
>     Rebase on top of kernel 5.6-rc1.
> 
>  arch/mips/boot/dts/ingenic/ci20.dts | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts 
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 37b9316..98c4c42 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -456,6 +456,13 @@
> 
>  &tcu {
>  	/* 3 MHz for the system timer and clocksource */
> -	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
> -	assigned-clock-rates = <3000000>, <3000000>;
> +	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
> +					  <&tcu TCU_CLK_TIMER2>;
> +	assigned-clock-rates = <3000000>, <3000000>, <750000>;
> +
> +	/*
> +	 * Use channel #0 and #1 for the per core system timer,
> +	 * and use channel #2 for the clocksource.
> +	 */
> +	ingenic,pwm-channels-mask = <0xF8>;
>  };
> --
> 2.7.4
>