[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CACRpkdZ7uq4U6GBQQQh=pTLf4wW3KfH3Zrz9z_3ZQgoaJD9Ynw@mail.gmail.com>
Date: Thu, 20 Feb 2020 10:04:11 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Alexandre Torgue <alexandre.torgue@...com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <maz@...nel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
Marek Vasut <marex@...x.de>
Subject: Re: [PATCH v3 2/2] pinctrl: stm32: Add level interrupt support to
gpio irq chip
On Wed, Feb 19, 2020 at 3:32 PM Alexandre Torgue
<alexandre.torgue@...com> wrote:
> GPIO hardware block is directly linked to EXTI block but EXTI handles
> external interrupts only on edge. To be able to handle GPIO interrupt on
> level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip)
> is retriggered following interrupt type and gpio line value.
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@...com>
> Tested-by: Marek Vasut <marex@...x.de>
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>
If Marc want to merge it with patch 1/2 go ahead!
Alternatively I can merge both patches.
Thanks to you & Marek for hashing this out, excellent work!
Yours,
Linus Walleij
Powered by blists - more mailing lists