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Message-ID: <158228107291.28353.2579324041035414462.tip-bot2@tip-bot2>
Date: Fri, 21 Feb 2020 10:31:12 -0000
From: "tip-bot2 for Zenghui Yu" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Zenghui Yu <yuzenghui@...wei.com>,
Thomas Gleixner <tglx@...utronix.de>, stable@...r.kernel.org,
x86 <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: [tip: irq/urgent] genirq/irqdomain: Make sure all irq domain flags
are distinct
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 2546287c5fb363a0165933ae2181c92f03e701d0
Gitweb: https://git.kernel.org/tip/2546287c5fb363a0165933ae2181c92f03e701d0
Author: Zenghui Yu <yuzenghui@...wei.com>
AuthorDate: Fri, 21 Feb 2020 10:07:25 +08:00
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Fri, 21 Feb 2020 11:29:15 +01:00
genirq/irqdomain: Make sure all irq domain flags are distinct
This was noticed when printing debugfs for MSIs on my ARM64 server. The
new dstate IRQD_MSI_NOMASK_QUIRK came out surprisingly while it should only
be the x86 stuff for the time being...
The new MSI quirk flag uses the same bit as IRQ_DOMAIN_NAME_ALLOCATED which
is oddly defined as bit 6 for no good reason.
Switch it to the non used bit 1.
Fixes: 6f1a4891a592 ("x86/apic/msi: Plug non-maskable MSI affinity race")
Signed-off-by: Zenghui Yu <yuzenghui@...wei.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: stable@...r.kernel.org
Link: https://lkml.kernel.org/r/20200221020725.2038-1-yuzenghui@huawei.com
---
include/linux/irqdomain.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
index b2d4757..8d062e8 100644
--- a/include/linux/irqdomain.h
+++ b/include/linux/irqdomain.h
@@ -192,7 +192,7 @@ enum {
IRQ_DOMAIN_FLAG_HIERARCHY = (1 << 0),
/* Irq domain name was allocated in __irq_domain_add() */
- IRQ_DOMAIN_NAME_ALLOCATED = (1 << 6),
+ IRQ_DOMAIN_NAME_ALLOCATED = (1 << 1),
/* Irq domain is an IPI domain with virq per cpu */
IRQ_DOMAIN_FLAG_IPI_PER_CPU = (1 << 2),
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