linux-kernel - Re: [PATCH v2] ARM: dts: sun8i-a83t: Add thermal trip points/cooling maps

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <2e4213a6-2aaf-641c-f741-9503f3ffd5fe@linaro.org>
Date:   Mon, 24 Feb 2020 18:06:20 +0100
From:   Daniel Lezcano <daniel.lezcano@...aro.org>
To:     Ondrej Jirman <megous@...ous.com>, linux-sunxi@...glegroups.com
Cc:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Maxime Ripard <mripard@...nel.org>,
        Chen-Yu Tsai <wens@...e.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/Allwinner sunXi SoC support" 
        <linux-arm-kernel@...ts.infradead.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] ARM: dts: sun8i-a83t: Add thermal trip points/cooling
 maps

On 24/02/2020 17:54, Ondrej Jirman wrote:
> This enables passive cooling by down-regulating CPU voltage
> and frequency.
> 
> For the trip points, I used values from the BSP code directly.
> 
> The critical trip point value is 30°C above the maximum recommended
> ambient temperature (70°C) for the SoC from the datasheet, so there's
> some headroom even at such a high ambient temperature.
> 
> Signed-off-by: Ondrej Jirman <megous@...ous.com>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 60 +++++++++++++++++++++++++++----
>  1 file changed, 54 insertions(+), 6 deletions(-)
> 
> v2:
> - added more detail to the commit description
> 
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 74ac7ee9383cf..53c2b6a836f27 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -72,7 +72,7 @@ cpu0: cpu@0 {
>  			#cooling-cells = <2>;
>  		};
>  
> -		cpu@1 {
> +		cpu1: cpu@1 {
>  			compatible = "arm,cortex-a7";
>  			device_type = "cpu";
>  			clocks = <&ccu CLK_C0CPUX>;
> @@ -83,7 +83,7 @@ cpu@1 {
>  			#cooling-cells = <2>;
>  		};
>  
> -		cpu@2 {
> +		cpu2: cpu@2 {
>  			compatible = "arm,cortex-a7";
>  			device_type = "cpu";
>  			clocks = <&ccu CLK_C0CPUX>;
> @@ -94,7 +94,7 @@ cpu@2 {
>  			#cooling-cells = <2>;
>  		};
>  
> -		cpu@3 {
> +		cpu3: cpu@3 {
>  			compatible = "arm,cortex-a7";
>  			device_type = "cpu";
>  			clocks = <&ccu CLK_C0CPUX>;
> @@ -116,7 +116,7 @@ cpu100: cpu@100 {
>  			#cooling-cells = <2>;
>  		};
>  
> -		cpu@101 {
> +		cpu101: cpu@101 {
>  			compatible = "arm,cortex-a7";
>  			device_type = "cpu";
>  			clocks = <&ccu CLK_C1CPUX>;
> @@ -127,7 +127,7 @@ cpu@101 {
>  			#cooling-cells = <2>;
>  		};
>  
> -		cpu@102 {
> +		cpu102: cpu@102 {
>  			compatible = "arm,cortex-a7";
>  			device_type = "cpu";
>  			clocks = <&ccu CLK_C1CPUX>;
> @@ -138,7 +138,7 @@ cpu@102 {
>  			#cooling-cells = <2>;
>  		};
>  
> -		cpu@103 {
> +		cpu103: cpu@103 {
>  			compatible = "arm,cortex-a7";
>  			device_type = "cpu";
>  			clocks = <&ccu CLK_C1CPUX>;
> @@ -1188,12 +1188,60 @@ cpu0_thermal: cpu0-thermal {
>  			polling-delay-passive = <0>;
>  			polling-delay = <0>;
>  			thermal-sensors = <&ths 0>;
> +
> +			trips {
> +				cpu0_hot: cpu-hot {
> +					temperature = <80000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				cpu0_very_hot: cpu-very-hot {
> +					temperature = <100000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +				cpu-hot-limit {
> +					trip = <&cpu0_hot>;
> +					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu1_thermal: cpu1-thermal {
>  			polling-delay-passive = <0>;

No polling to mitigate?

>  			polling-delay = <0>;
>  			thermal-sensors = <&ths 1>;
> +
> +			trips {
> +				cpu1_hot: cpu-hot {
> +					temperature = <80000>;
> +					hysteresis = <2000>;
> +					type = "passive";

I'm curious, can you really reach this temperature with a cortex-a7
running at 1.2GHz max?

> +				};
> +
> +				cpu1_very_hot: cpu-very-hot {
> +					temperature = <100000>;
> +					hysteresis = <0>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +				cpu-hot-limit {
> +					trip = <&cpu1_hot>;
> +					cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		gpu_thermal: gpu-thermal {
> 


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog