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Date: Wed, 26 Feb 2020 16:19:56 -0600 From: Rob Herring <robh@...nel.org> To: Grygorii Strashko <grygorii.strashko@...com> Cc: Kishon Vijay Abraham I <kishon@...com>, Tero Kristo <t-kristo@...com>, "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org, Sekhar Nori <nsekhar@...com>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, Rob Herring <robh+dt@...nel.org>, Grygorii Strashko <grygorii.strashko@...com> Subject: Re: [for-next PATCH 2/5] dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc On Sat, 22 Feb 2020 14:03:55 +0200, Grygorii Strashko wrote: > TI AM654x/J721E SoCs have the same PHY interface selection mechanism for > CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields > placement is different. > > This patch adds corresponding compatible strings to enable support for TI > AM654x/J721E SoCs. > > Signed-off-by: Grygorii Strashko <grygorii.strashko@...com> > --- > Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@...nel.org>
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