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Message-ID: <6355f1fd-b929-730e-e0f6-96dd5100e3f9@collabora.com>
Date: Wed, 26 Feb 2020 10:24:04 +0100
From: Enric Balletbo i Serra <enric.balletbo@...labora.com>
To: CK Hu <ck.hu@...iatek.com>
Cc: mark.rutland@....com, Kate Stewart <kstewart@...uxfoundation.org>,
Minghsiu Tsai <minghsiu.tsai@...iatek.com>,
Andrew-CT Chen <andrew-ct.chen@...iatek.com>, airlied@...ux.ie,
mturquette@...libre.com, dri-devel@...ts.freedesktop.org,
Richard Fontana <rfontana@...hat.com>,
laurent.pinchart@...asonboard.com, ulrich.hecht+renesas@...il.com,
Collabora Kernel ML <kernel@...labora.com>,
linux-clk@...r.kernel.org, Nicolas Boichat <drinkcat@...omium.org>,
Weiyi Lu <weiyi.lu@...iatek.com>,
Krzysztof Kozlowski <krzk@...nel.org>, wens@...e.org,
Allison Randal <allison@...utok.net>,
mtk01761 <wendell.lin@...iatek.com>,
Owen Chen <owen.chen@...iatek.com>,
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p.zabel@...gutronix.de, frank-w@...lic-files.de,
Seiya Wang <seiya.wang@...iatek.com>, sean.wang@...iatek.com,
Houlong Wei <houlong.wei@...iatek.com>, robh+dt@...nel.org,
linux-mediatek@...ts.infradead.org, hsinyi@...omium.org,
Matthias Brugger <"matthias. bgg"@gmail.com>,
Thomas Gleixner <tglx@...utronix.de>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
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rdunlap@...radead.org, linux-kernel@...r.kernel.org,
Daniel Vetter <daniel@...ll.ch>, matthias.bgg@...nel.org
Subject: Re: [PATCH v8 0/6] arm/arm64: mediatek: Fix mmsys device probing
Hi CK,
On 26/2/20 6:32, CK Hu wrote:
[snip]
>>
>> How do you see move mmsys to drivers/soc/mediatek and instantiate the clk and
>> mediatek-drm driver
>>
>> mmsys: syscon@...00000 {
>> compatible = "mediatek,mt8173-mmsys", "syscon", "simple-mfd";
>> reg = <0 0x14000000 0 0x1000>;
>> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
>>
>> clock-controller {
>> compatible = "mediatek,clk-mt8173-mm"
>> assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
>> assigned-clock-rates = <400000000>;
>> #clock-cells = <1>;
>> };
>>
>> display-subsystem {
>> compatible = "mediatek,display-subsystem";
>> };
>> };
>>
>
> Let's start with the simple definition.
>
> mmsys: syscon at 14000000 {
> compatible = "mediatek,mt8173-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
> assigned-clock-rates = <400000000>;
> #clock-cells = <1>;
> };
>
> When we break clock control to a sub device of mmsys, the reason is that
> 'Linux' generally categorize clock controller to a device. When we break
> display control to a sub device of mmsys, the reason is that 'Linux'
> generally categorize display controller to a device. All these seems
> software-oriented reason, so I think we do not break any sub device and
> keep mmsys simple.
>
> When I search of_clk_add_provider(), I find that not all clock provider
> code is in drivers/clk. Maybe when a clock controller is not an
> independent device, the driver code of clock controller could be placed
> within the device driver it belonged to. We could place mmsys driver in
> drivers/soc/mediatek/, and it control the clock, routing, fake engine,
> memory delay,.... I would like drm driver to be placed in
> drivers/gpu/drm/ because display function block, such as OVL, does not
> belong to mmsys device. And finally let mmsys driver to probe
> mediatek-drm driver.
>
You can apply the same reasoning in the clk subsystem, not all the drivers in
drivers/clk are pure clock controllers, some of them are already
system-controller or "simple-mfd" and some of them even instantiate other
subdrivers via the platform register API.
Note that moving clk-<chip>-mm drivers to drivers/soc/mediatek will imply move a
lot of code, I'll focus only on mt8173 for now because is the only platform I
can really test. Let me prepare a v9 and lets see how looks like.
Thanks,
Enric
> Regards,
> CK
[snip]
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