linux-kernel - Re: [RFC 00/11] perf: Enhancing perf to export processor hazard information

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Message-ID: <20200302101332.GS18400@hirez.programming.kicks-ass.net>
Date:   Mon, 2 Mar 2020 11:13:32 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     Ravi Bangoria <ravi.bangoria@...ux.ibm.com>
Cc:     linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org,
        eranian@...gle.com, mpe@...erman.id.au, paulus@...ba.org,
        mingo@...hat.com, acme@...nel.org, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, jolsa@...hat.com,
        namhyung@...nel.org, adrian.hunter@...el.com, ak@...ux.intel.com,
        kan.liang@...ux.intel.com, alexey.budankov@...ux.intel.com,
        yao.jin@...ux.intel.com, robert.richter@....com,
        kim.phillips@....com, maddy@...ux.ibm.com
Subject: Re: [RFC 00/11] perf: Enhancing perf to export processor hazard
 information

On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote:
> Modern processors export such hazard data in Performance
> Monitoring Unit (PMU) registers. Ex, 'Sampled Instruction Event
> Register' on IBM PowerPC[1][2] and 'Instruction-Based Sampling' on
> AMD[3] provides similar information.
> 
> Implementation detail:
> 
> A new sample_type called PERF_SAMPLE_PIPELINE_HAZ is introduced.
> If it's set, kernel converts arch specific hazard information
> into generic format:
> 
>   struct perf_pipeline_haz_data {
>          /* Instruction/Opcode type: Load, Store, Branch .... */
>          __u8    itype;
>          /* Instruction Cache source */
>          __u8    icache;
>          /* Instruction suffered hazard in pipeline stage */
>          __u8    hazard_stage;
>          /* Hazard reason */
>          __u8    hazard_reason;
>          /* Instruction suffered stall in pipeline stage */
>          __u8    stall_stage;
>          /* Stall reason */
>          __u8    stall_reason;
>          __u16   pad;
>   };

Kim, does this format indeed work for AMD IBS?