linux-kernel - [PATCH] dra7: sata: Fix SATA with CONFIG_ARM

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Date:   Wed, 4 Mar 2020 11:00:31 +0200
From:   Roger Quadros <rogerq@...com>
To:     <tony@...mide.com>
CC:     <yan-liu@...com>, <linux-omap@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Roger Quadros <rogerq@...com>, Christoph Hellwig <hch@....de>,
        Robin Murphy <robin.murphy@....com>,
        Rob Herring <robh+dt@...nel.org>
Subject: [PATCH] dra7: sata: Fix SATA with CONFIG_ARM_LPAE enabled

Even though the TRM says that SATA IP has 36 address bits
wired in the SoC, we see bus errors whenever any address
greater than 32-bit is given to the controller.

This happens on dra7-EVM with 4G of RAM with CONFIG_ARM_LPAE=y.

As a workaround we limit the DMA address range to 32-bits
for SATA.

Cc: Christoph Hellwig <hch@....de>
Cc: Robin Murphy <robin.murphy@....com>
Cc: Rob Herring <robh+dt@...nel.org>
Reported-by: Yan Liu <yan-liu@...com>
Signed-off-by: Roger Quadros <rogerq@...com>
---

NOTE: Currently ARM dma-mapping code doesn't account for devices
bus_dma_limit. This is fixed in [1].

[1] https://lkml.org/lkml/2020/2/18/712

 arch/arm/boot/dts/dra7.dtsi | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d78b684e7fca..895462c22d1c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -642,15 +642,22 @@
 		};
 
 		/* OCP2SCP3 */
-		sata: sata@...41100 {
-			compatible = "snps,dwc-ahci";
-			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
-			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&sata_phy>;
-			phy-names = "sata-phy";
-			clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
-			ti,hwmods = "sata";
-			ports-implemented = <0x1>;
+		sata_aux_bus {
+			#address-cells = <1>;
+			#size-cells = <2>;
+			compatible = "simple-bus";
+			ranges = <0x0 0x4a140000 0x0 0x1200>;
+			dma-ranges = <0x0 0x0 0x1 0x00000000>;
+			sata: sata@...41100 {
+				compatible = "snps,dwc-ahci";
+				reg = <0x0 0x0 0x1100>, <0x1100 0x0 0x7>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&sata_phy>;
+				phy-names = "sata-phy";
+				clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
+				ti,hwmods = "sata";
+				ports-implemented = <0x1>;
+			};
 		};
 
 		/* OCP2SCP1 */
-- 
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