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Message-ID: <20200311214432.GA5900@alpha.franken.de>
Date:   Wed, 11 Mar 2020 22:44:32 +0100
From:   Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     Kamal Dasu <kdasu.kdev@...il.com>, linux-mips@...r.kernel.org,
        bcm-kernel-feedback-list@...adcom.com,
        Ralf Baechle <ralf@...ux-mips.org>,
        Paul Burton <paulburton@...nel.org>,
        James Hogan <jhogan@...nel.org>,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        Huacai Chen <chenhc@...ote.com>,
        Mike Rapoport <rppt@...ux.ibm.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

On Wed, Mar 11, 2020 at 01:54:23PM -0700, Florian Fainelli wrote:
> On 2/7/20 2:33 PM, Kamal Dasu wrote:
> > Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> > line can contain two instruction cache lines (64B), or four data cache
> > lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> > ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> > secondary cache module (ZSCM) on DMA from device so that data returned is
> > coherent during DMA read operations.
> > 
> > Signed-off-by: Kamal Dasu <kdasu.kdev@...il.com>
> 
> Thomas can review and apply this patch? Thank you!

looks good to me. I only wonder whether r4k_dma_cache_wbinv() also
needs this ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

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