linux-kernel - Re: [PATCH v28 14/22] selftests/x86: Add a selftest for SGX

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20200311132832.GA75185@linux.intel.com>
Date:   Wed, 11 Mar 2020 15:28:32 +0200
From:   Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>
To:     Nathaniel McCallum <npmccallum@...hat.com>
Cc:     linux-kernel@...r.kernel.org, x86@...nel.org,
        linux-sgx@...r.kernel.org, akpm@...ux-foundation.org,
        dave.hansen@...el.com,
        "Christopherson, Sean J" <sean.j.christopherson@...el.com>,
        Neil Horman <nhorman@...hat.com>,
        "Huang, Haitao" <haitao.huang@...el.com>,
        andriy.shevchenko@...ux.intel.com, tglx@...utronix.de,
        "Svahn, Kai" <kai.svahn@...el.com>, bp@...en8.de,
        Josh Triplett <josh@...htriplett.org>, luto@...nel.org,
        kai.huang@...el.com, rientjes@...gle.com, cedric.xing@...el.com,
        Patrick Uiterwijk <puiterwijk@...hat.com>,
        linux-kselftest@...r.kernel.org
Subject: Re: [PATCH v28 14/22] selftests/x86: Add a selftest for SGX

On Thu, Mar 05, 2020 at 01:33:28PM +0200, Jarkko Sakkinen wrote:
> On Wed, 2020-03-04 at 14:27 -0500, Nathaniel McCallum wrote:
> > > > +xsave_area:
> > > +       .fill   1, 4, 0x037F            # FCW
> > > +       .fill   5, 4, 0
> > > +       .fill   1, 4, 0x1F80            # MXCSR
> > > +       .fill   1, 4, 0xFFFF            # MXCSR_MASK
> > > +       .fill   123, 4, 0
> > > +       .fill   1, 4, 0x80000000        # XCOMP_BV[63] = 1, compaction mode
> > > +       .fill   12, 4, 0
> > 
> > I find this much more readable:
> 
> And I always aim to get things more readable. Thank you.
> 
> > xsave_area:
> >         # Legacy
> >         .fill   1, 4, 0x037F            # FCW
> >         .fill   5, 4, 0
> >         .fill   1, 4, 0x1F80            # MXCSR
> >         .fill   1, 4, 0xFFFF            # MXCSR_MASK
> >         .fill   60, 8, 0
> > 
> >         # Header
> >         .fill   1, 8, 0                 # XSTATE_BV
> >         .fill   1, 8, 1 << 63           # XCOMP_BV (compaction mode)
> >         .fill   6, 8, 0
> > 
> > Also, since people are likely to copy this code for their own
> > enclaves, it would be helpful to document which flags are set in FCW
> > and MXCSR.
> 
> It was meant as a test program but I'd guess what you say is true
> because it also might be the only alternative user space to Intel's
> :-) And a great starting point if you want to do things from scratch.
> 
> Because I meant it as a smoke test program for SGX, not everything is
> too well documented but given the multipurpose use for that code I'll
> make the improvements that you are suggesting.

For FPU Control World (FCW), I think 0x037F is not the right value even
if section 18.5 in the x86 SDM says that it is the initial value for it.

I took that value from that section.

The reason I think that there is an error in the SDM is that if you look
at the section 8.1.5, you'll see that bit 6 is a reserved bit. Thus,
does not make to set it on.

I think the legit value ought to be 0x33F i.e. unset bit 6.

In any case check:

https://raw.githubusercontent.com/jsakkine-intel/linux-sgx/master/tools/testing/selftests/x86/sgx/encl_bootstrap.S

I.e. both have now a reference:

1. To the section that describes the default.
2. To the section that describes what the bits mean.

/Jarkko