linux-kernel - Re: [PATCH 2/3 RESEND] perf/amd/uncore: Prepare L3 thread mask code for Family 19h support

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Message-ID: <20200312141216.GD15619@zn.tnic>
Date:   Thu, 12 Mar 2020 15:12:16 +0100
From:   Borislav Petkov <bp@...en8.de>
To:     Kim Phillips <kim.phillips@....com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...nel.org>, Ingo Molnar <mingo@...hat.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>, Jiri Olsa <jolsa@...hat.com>,
        Mark Rutland <mark.rutland@....com>,
        Michael Petlan <mpetlan@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        linux-kernel@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH 2/3 RESEND] perf/amd/uncore: Prepare L3 thread mask code
 for Family 19h support

On Wed, Mar 11, 2020 at 02:13:22PM -0500, Kim Phillips wrote:
> In order to better accommodate the upcoming Family 19h support,
> given the 80-char line limit, we move the existing code into a new
> l3_thread_slice_mask function, and convert it to use the more
> readable topology_* helper functions.
> 
> Signed-off-by: Kim Phillips <kim.phillips@....com>
> Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
> Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
> Cc: Borislav Petkov <bp@...en8.de>
> Cc: "H. Peter Anvin" <hpa@...or.com>
> Cc: Ingo Molnar <mingo@...nel.org>
> Cc: Ingo Molnar <mingo@...hat.com>
> Cc: Jiri Olsa <jolsa@...hat.com>
> Cc: Mark Rutland <mark.rutland@....com>
> Cc: Michael Petlan <mpetlan@...hat.com>
> Cc: Namhyung Kim <namhyung@...nel.org>
> Cc: Peter Zijlstra <peterz@...radead.org>
> Cc: Thomas Gleixner <tglx@...utronix.de>
> Cc: linux-kernel@...r.kernel.org
> Cc: x86@...nel.org
> ---
> RESEND.  No changes since original submission 19 Feb 2020:
> 
> https://lkml.org/lkml/2020/2/19/1192
> 
>  arch/x86/events/amd/uncore.c | 28 +++++++++++++++++++---------
>  1 file changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
> index 4d867a752f0e..e635c40ca9c4 100644
> --- a/arch/x86/events/amd/uncore.c
> +++ b/arch/x86/events/amd/uncore.c
> @@ -180,6 +180,23 @@ static void amd_uncore_del(struct perf_event *event, int flags)
>  	hwc->idx = -1;
>  }
>  
> +/*
> + * Convert logical cpu number to L3 PMC Config ThreadMask format
> + */
> +static u64 l3_thread_slice_mask(int cpu)
> +{
> +	unsigned int shift, thread = 0;
> +	u64 thread_mask, core = topology_core_id(cpu);
> +
> +	if (topology_smt_supported() && !topology_is_primary_thread(cpu))
> +		thread = 1;
> +
> +	shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
> +	thread_mask = BIT_ULL(shift);
> +
> +	return AMD64_L3_SLICE_MASK | thread_mask;
> +}
> +
>  static int amd_uncore_event_init(struct perf_event *event)
>  {
>  	struct amd_uncore *uncore;
> @@ -206,15 +223,8 @@ static int amd_uncore_event_init(struct perf_event *event)
>  	 * SliceMask and ThreadMask need to be set for certain L3 events in
>  	 * Family 17h. For other events, the two fields do not affect the count.
>  	 */
> -	if (l3_mask && is_llc_event(event)) {
> -		int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4);
> -
> -		if (smp_num_siblings > 1)
> -			thread += cpu_data(event->cpu).apicid & 1;
> -
> -		hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) &
> -				AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK;
> -	}
> +	if (l3_mask && is_llc_event(event))
> +		hwc->config |= l3_thread_slice_mask(event->cpu);
>  
>  	uncore = event_to_amd_uncore(event);
>  	if (!uncore)
> -- 

If you carve out functionality into a separate function and then do
changes to that functionality, you do two patches: the first one is
doing only the mechanical move only and the second one does the changes.

Please do that with that one too.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette