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Message-ID: <20200313212345.GM4751@pendragon.ideasonboard.com>
Date: Fri, 13 Mar 2020 23:23:45 +0200
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Cc: Mauro Carvalho Chehab <mchehab@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
NXP Linux Team <linux-imx@....com>,
Magnus Damm <magnus.damm@...il.com>,
Ezequiel Garcia <ezequiel@...labora.com>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
Fabio Estevam <festevam@...il.com>,
linux-media@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3 3/4] media: i2c: ov5645: Set maximum leverage of
external clock frequency to 24480000
Hi Prabhakar,
Thank you for the patch.
On Fri, Mar 13, 2020 at 09:12:33PM +0000, Lad Prabhakar wrote:
> While testing on Renesas RZ/G2E platform, noticed the clock frequency to
> be 24242424 as a result the probe failed. However increasing the maximum
> leverage of external clock frequency to 24480000 fixes this issue. Since
> this difference is small enough and is insignificant set the same in the
> driver.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> drivers/media/i2c/ov5645.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/i2c/ov5645.c b/drivers/media/i2c/ov5645.c
> index 4fbabf3..b49359b 100644
> --- a/drivers/media/i2c/ov5645.c
> +++ b/drivers/media/i2c/ov5645.c
> @@ -1107,8 +1107,10 @@ static int ov5645_probe(struct i2c_client *client)
> }
>
> xclk_freq = clk_get_rate(ov5645->xclk);
> - /* external clock must be 24MHz, allow 1% tolerance */
> - if (xclk_freq < 23760000 || xclk_freq > 24240000) {
> + /* external clock must be 24MHz, allow a minimum 1% and a maximum of 2%
> + * tolerance
So where do these numbers come from ? I understand that 2% is what you
need to make your clock fit in the range, but why -1%/+2% instead of
-2%/+2% ? And why not 2.5 or 3% ? The sensor datasheet documents the
range of supported xvclk frequencies to be 6MHz to 54MHz. I understand
that PLL parameters depend on the clock frequency, but could they be
calculated instead of hardcoded, to avoid requiring an exact 24MHz input
frequency ?
> + */
> + if (xclk_freq < 23760000 || xclk_freq > 24480000) {
> dev_err(dev, "external clock frequency %u is not supported\n",
> xclk_freq);
> return -EINVAL;
--
Regards,
Laurent Pinchart
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