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Message-ID: <20200314081312.GA4948@afzalpc>
Date: Sat, 14 Mar 2020 13:43:12 +0530
From: afzal mohammed <afzal.mohd.ma@...il.com>
To: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc: Nathan Chancellor <natechancellor@...il.com>,
linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paulburton@...nel.org>,
Florian Fainelli <f.fainelli@...il.com>,
bcm-kernel-feedback-list@...adcom.com,
"Maciej W. Rozycki" <macro@...ux-mips.org>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
Keguang Zhang <keguang.zhang@...il.com>,
Huacai Chen <chenhc@...ote.com>,
John Crispin <john@...ozen.org>
Subject: [PATCH v2] MIPS: pass non-NULL dev_id on shared request_irq()
Recently all usages of setup_irq() was replaced by request_irq().
request_irq() does a few sanity checks that were not done in
setup_irq(), if they fail irq registration will fail. One of the check
is to ensure that non-NULL dev_id is passed in the case of shared irq.
This caused malta on qemu to hang.
Fix it by passing handler as dev_id to all request_irq()'s that are
shared. For sni, instead of passing non-NULL dev_id, remove shared irq
flags.
Fixes: ac8fd122e070 ("MIPS: Replace setup_irq() by request_irq()")
Reported-by: Nathan Chancellor <natechancellor@...il.com>
Suggested-by: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Signed-off-by: afzal mohammed <afzal.mohd.ma@...il.com>
---
v2:
* use handler for dev_id
* remove shared irq flags for sni
arch/mips/dec/setup.c | 2 +-
arch/mips/kernel/cevt-r4k.c | 3 ++-
arch/mips/loongson2ef/lemote-2f/irq.c | 2 +-
arch/mips/pmcs-msp71xx/msp_time.c | 2 +-
arch/mips/sni/a20r.c | 4 ++--
arch/mips/sni/pcit.c | 8 ++++----
arch/mips/sni/rm200.c | 6 +++---
7 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index c8bbac0c5051..d4e868b828e5 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -758,7 +758,7 @@ void __init arch_init_irq(void)
/* Register the bus error interrupt. */
if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) {
if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler,
- busirq_flags, "bus error", NULL))
+ busirq_flags, "bus error", busirq_handler))
pr_err("Failed to register bus error interrupt\n");
}
/* Register the HALT interrupt. */
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 64e917dfe6b2..17a9cbb8b3df 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -292,7 +292,8 @@ int r4k_clockevent_init(void)
cp0_timer_irq_installed = 1;
- if (request_irq(irq, c0_compare_interrupt, flags, "timer", NULL))
+ if (request_irq(irq, c0_compare_interrupt, flags, "timer",
+ c0_compare_interrupt))
pr_err("Failed to request irq %d (timer)\n", irq);
return 0;
diff --git a/arch/mips/loongson2ef/lemote-2f/irq.c b/arch/mips/loongson2ef/lemote-2f/irq.c
index 34e15e8b7a8f..6f00579971a3 100644
--- a/arch/mips/loongson2ef/lemote-2f/irq.c
+++ b/arch/mips/loongson2ef/lemote-2f/irq.c
@@ -109,7 +109,7 @@ void __init mach_init_irq(void)
/* setup north bridge irq (bonito) */
if (request_irq(LOONGSON_NORTH_BRIDGE_IRQ, ip6_action,
- IRQF_SHARED | IRQF_NO_THREAD, "cascade", NULL))
+ IRQF_SHARED | IRQF_NO_THREAD, "cascade", ip6_action))
pr_err("Failed to register north bridge cascade interrupt\n");
/* setup source bridge irq (i8259) */
if (request_irq(LOONGSON_SOUTH_BRIDGE_IRQ, no_action,
diff --git a/arch/mips/pmcs-msp71xx/msp_time.c b/arch/mips/pmcs-msp71xx/msp_time.c
index baf0da8b4c98..9c629829f447 100644
--- a/arch/mips/pmcs-msp71xx/msp_time.c
+++ b/arch/mips/pmcs-msp71xx/msp_time.c
@@ -81,7 +81,7 @@ unsigned int get_c0_compare_int(void)
/* MIPS_MT modes may want timer for second VPE */
if ((get_current_vpe()) && !tim_installed) {
if (request_irq(MSP_INT_VPE1_TIMER, c0_compare_interrupt, flags,
- "timer", NULL))
+ "timer", c0_compare_interrupt))
pr_err("Failed to register timer interrupt\n");
tim_installed++;
}
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index ba966d62fb4b..0ecffb65fd6d 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -222,8 +222,8 @@ void __init sni_a20r_irq_init(void)
irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
sni_hwint = a20r_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
- if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler,
- IRQF_SHARED, "ISA", NULL))
+ if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",
+ NULL))
pr_err("Failed to register ISA interrupt\n");
}
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 4a850ab03398..b331fe22c529 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -244,8 +244,8 @@ void __init sni_pcit_irq_init(void)
*(volatile u32 *)SNI_PCIT_INT_REG = 0;
sni_hwint = sni_pcit_hwint;
change_c0_status(ST0_IM, IE_IRQ1);
- if (request_irq(SNI_PCIT_INT_START + 6, sni_isa_irq_handler,
- IRQF_SHARED, "ISA", NULL))
+ if (request_irq(SNI_PCIT_INT_START + 6, sni_isa_irq_handler, 0, "ISA",
+ NULL))
pr_err("Failed to register ISA interrupt\n");
}
@@ -259,8 +259,8 @@ void __init sni_pcit_cplus_irq_init(void)
*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
sni_hwint = sni_pcit_hwint_cplus;
change_c0_status(ST0_IM, IE_IRQ0);
- if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler,
- IRQF_SHARED, "ISA", NULL))
+ if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",
+ NULL))
pr_err("Failed to register ISA interrupt\n");
}
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index ba1f2fc6a43e..d84744ca871d 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -473,10 +473,10 @@ void __init sni_rm200_irq_init(void)
sni_hwint = sni_rm200_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
if (request_irq(SNI_RM200_INT_START + 0, sni_rm200_i8259A_irq_handler,
- IRQF_SHARED, "onboard ISA", NULL))
+ 0, "onboard ISA", NULL))
pr_err("Failed to register onboard ISA interrupt\n");
- if (request_irq(SNI_RM200_INT_START + 1, sni_isa_irq_handler,
- IRQF_SHARED, "ISA", NULL))
+ if (request_irq(SNI_RM200_INT_START + 1, sni_isa_irq_handler, 0, "ISA",
+ NULL))
pr_err("Failed to register ISA interrupt\n");
}
--
2.18.0
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