linux-kernel - Re: [PATCH v1 3/3] clk: qcom: gcc: Add support for Secure control source clock

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <158438098823.88485.2094714876575396381@swboyd.mtv.corp.google.com>
Date:   Mon, 16 Mar 2020 10:49:48 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Michael Turquette <mturquette@...libre.com>,
        Taniya Das <tdas@...eaurora.org>
Cc:     David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Andy Gross <agross@...nel.org>, devicetree@...r.kernel.org,
        robh@...nel.org, robh+dt@...nel.org,
        Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH v1 3/3] clk: qcom: gcc: Add support for Secure control source clock

Quoting Taniya Das (2020-03-16 03:54:42)
> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
> index ad75847..3302f19 100644
> --- a/drivers/clk/qcom/gcc-sc7180.c
> +++ b/drivers/clk/qcom/gcc-sc7180.c
> @@ -817,6 +817,26 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
>         },
>  };
> 
> +static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
> +       F(4800000, P_BI_TCXO, 4, 0, 0),
> +       F(19200000, P_BI_TCXO, 1, 0, 0),
> +       { }
> +};
> +
> +static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
> +       .cmd_rcgr = 0x3d030,
> +       .mnd_width = 0,
> +       .hid_width = 5,
> +       .parent_map = gcc_parent_map_3,
> +       .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
> +       .clkr.hw.init = &(struct clk_init_data){
> +               .name = "gcc_sec_ctrl_clk_src",
> +               .parent_data = gcc_parent_data_3,
> +               .num_parents = 3,

ARRAY_SIZE please.

> +               .ops = &clk_rcg2_ops,
> +       },
> +};
> +
>  static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
>         .halt_reg = 0x82024,
>         .halt_check = BRANCH_HALT_DELAY,