linux-kernel - Re: [PATCH 2/6] device/pci: add cmdmem cap to pci

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Date:   Tue, 31 Mar 2020 14:44:19 -0700
From:   Dave Jiang <dave.jiang@...el.com>
To:     Bjorn Helgaas <helgaas@...nel.org>
Cc:     vkoul@...nel.org, tglx@...utronix.de, mingo@...hat.com,
        bp@...en8.de, hpa@...or.com, gregkh@...uxfoundation.org,
        arnd@...db.de, linux-kernel@...r.kernel.org, x86@...nel.org,
        dmaengine@...r.kernel.org, dan.j.williams@...el.com,
        ashok.raj@...el.com, fenghua.yu@...el.com,
        linux-pci@...r.kernel.org, tony.luck@...el.com, jing.lin@...el.com,
        sanjay.k.kumar@...el.com
Subject: Re: [PATCH 2/6] device/pci: add cmdmem cap to pci_dev



On 3/31/2020 9:03 AM, Bjorn Helgaas wrote:
> On Mon, Mar 30, 2020 at 02:27:00PM -0700, Dave Jiang wrote:
>> Since the current accelerator devices do not have standard PCIe capability
>> enumeration for accepting ENQCMDS yet, for now an attribute of pdev->cmdmem has
>> been added to struct pci_dev.  Currently a PCI quirk must be used for the
>> devices that have such cap until the PCI cap is standardized. Add a helper
>> function to provide the check if a device supports the cmdmem capability.
>>
>> Such capability is expected to be added to PCIe device cap enumeration in
>> the future.

Re-send. My misconfigured mail client caused mailing lists to bounce the 
send.

> 
> This needs some sort of thumbnail description of what "synchronous
> write notification" and "cmdmem" mean.

I will add more explanation.

> 
> Do you have a pointer to a PCI-SIG ECR or similar?



Deferrable Memory Write (DMWr) ECR


https://members.pcisig.com/wg/PCI-SIG/document/13747

 From what I'm told it should be available for public review by EOW.

> 
> Your window size seems to be 85 or so.  It would be easier if you used
> 80 and wrapped the commit log to fit in 75 columns so it looks decent
> when "git log" indents it by 4.
> 
Ok I will fix.