linux-kernel - Re: [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <428968f6-d4ba-7b64-a2b0-59177c6a6be7@arm.com>
Date:   Thu, 2 Apr 2020 08:08:05 +0530
From:   Anshuman Khandual <anshuman.khandual@....com>
To:     Suzuki K Poulose <suzuki.poulose@....com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     catalin.marinas@....com, will@...nel.org,
        linux-kernel@...r.kernel.org, mark.rutland@....com
Subject: Re: [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in
 ID_PFR0 register



On 03/20/2020 11:37 PM, Suzuki K Poulose wrote:
> Cc: Mark Rutland

Sure, will add this to all the patches here. Also add 'Suggested-by'
tags on all the changes proposed by Mark. Should have already added
that in this version as well, my bad.

> 
> On 01/28/2020 12:39 PM, Anshuman Khandual wrote:
>> Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487E.a
>> specification. Except RAS and AMU, all other feature bits are now enabled.
>>
>> Cc: Catalin Marinas <catalin.marinas@....com>
>> Cc: Will Deacon <will@...nel.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@....com>
>> Cc: linux-kernel@...r.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>
> 
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@....com>
> 
>> ---
>>   arch/arm64/include/asm/sysreg.h | 3 +++
>>   arch/arm64/kernel/cpufeature.c  | 2 ++
>>   2 files changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 054aab7ebf1b..469d61c8fabf 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -718,6 +718,9 @@
>>   #define ID_ISAR6_DP_SHIFT        4
>>   #define ID_ISAR6_JSCVT_SHIFT        0
>>   +#define ID_PFR0_DIT_SHIFT        24
>> +#define ID_PFR0_CSV2_SHIFT        16
>> +
>>   #define ID_PFR2_SSBS_SHIFT        4
>>   #define ID_PFR2_CSV3_SHIFT        0
>>   diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index c1e837fc8f97..9e4dab15c608 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -341,6 +341,8 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
>>   };
>>     static const struct arm64_ftr_bits ftr_id_pfr0[] = {
>> +    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
>> +    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),        /* State3 */
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),        /* State2 */
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* State1 */
>>
> 
>