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Message-Id: <20200402000234.226466-4-helen.koike@collabora.com>
Date: Wed, 1 Apr 2020 21:02:33 -0300
From: Helen Koike <helen.koike@...labora.com>
To: devicetree@...r.kernel.org, linux-media@...r.kernel.org,
linux-rockchip@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org, devel@...verdev.osuosl.org,
robh+dt@...nel.org, heiko@...ech.de, hverkuil-cisco@...all.nl,
kernel@...labora.com, dafna.hirschfeld@...labora.com,
ezequiel@...labora.com, mark.rutland@....com,
karthik.poduval@...il.com
Subject: [PATCH 3/4] arm64: dts: rockchip: add rx0 mipi-phy for rk3399
From: Shunqian Zheng <zhengsq@...k-chips.com>
Designware MIPI D-PHY, used for ISP0 in rk3399.
Verified with:
make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml
Signed-off-by: Shunqian Zheng <zhengsq@...k-chips.com>
Signed-off-by: Jacob Chen <jacob2.chen@...k-chips.com>
Signed-off-by: Helen Koike <helen.koike@...labora.com>
---
This patchset came from the original ISP series from Rockchip:
https://patchwork.kernel.org/patch/10267409/
The only difference is:
- add phy-cells
- update compatible to "rockchip,rk3399-mipi-dphy-rx0"
- commit message
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 33cc21fcf4c10..fc0295d2a65a1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1394,6 +1394,17 @@ io_domains: io-domains {
status = "disabled";
};
+ mipi_dphy_rx0: mipi-dphy-rx0 {
+ compatible = "rockchip,rk3399-mipi-dphy-rx0";
+ clocks = <&cru SCLK_MIPIDPHY_REF>,
+ <&cru SCLK_DPHY_RX0_CFG>,
+ <&cru PCLK_VIO_GRF>;
+ clock-names = "dphy-ref", "dphy-cfg", "grf";
+ power-domains = <&power RK3399_PD_VIO>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@...0 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
--
2.26.0
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