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Message-ID: <87y2r6j1pn.fsf@nanos.tec.linutronix.de>
Date: Wed, 08 Apr 2020 01:49:40 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: "Singh\, Balbir" <sblbir@...zon.com>,
"keescook\@chromium.org" <keescook@...omium.org>
Cc: "linux-kernel\@vger.kernel.org" <linux-kernel@...r.kernel.org>,
"tony.luck\@intel.com" <tony.luck@...el.com>,
"benh\@kernel.crashing.org" <benh@...nel.crashing.org>,
"jpoimboe\@redhat.com" <jpoimboe@...hat.com>,
"x86\@kernel.org" <x86@...nel.org>,
"dave.hansen\@intel.com" <dave.hansen@...el.com>
Subject: Re: [PATCH v2 3/4] arch/x86: Optionally flush L1D on context switch
"Singh, Balbir" <sblbir@...zon.com> writes:
> On Tue, 2020-04-07 at 11:26 -0700, Kees Cook wrote:
>> On Mon, Apr 06, 2020 at 01:19:45PM +1000, Balbir Singh wrote:
>> > Add arch specific prctl()'s to opt-in to the L1D cache on context switch
>> > out, the existing mechanisms of tracking prev_mm via cpu_tlbstate is
>> > reused. cond_ibpb() is refactored and renamed into cond_mitigation().
>>
>> I still think this should be a generic prctl(). If there is a strong
>> reason not to do this, can it be described in the commit log here?
>
> I can move to prctl() if that is what you prefer, the prctl() can then do arch
> specific things. I thought in my question around would other arch's like to do
> this, I did not hear anything specific, but I am happy to convert the
> interface over.
Yes, please. It's just a matter of time that other architectures find
this useful. L1D attacks are not restricted to x86 AFAICT.
Thanks,
tglx
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