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Message-ID: <CAD=FV=W9swvzfCX5H=qhqdsnCAFTCWwzibcu72JJ9VKi9cR+1Q@mail.gmail.com>
Date: Tue, 14 Apr 2020 13:39:15 -0700
From: Doug Anderson <dianders@...omium.org>
To: Stephen Boyd <swboyd@...omium.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Maulik Shah <mkshah@...eaurora.org>,
Joe Perches <joe@...ches.com>,
Matthias Kaehlcke <mka@...omium.org>,
Evan Green <evgreen@...omium.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 2/2] soc: qcom: rpmh-rsc: Timeout after 1 second in write_tcs_reg_sync()
Hi,
On Tue, Apr 14, 2020 at 1:30 PM Stephen Boyd <swboyd@...omium.org> wrote:
>
> Quoting Douglas Anderson (2020-04-14 13:10:16)
> > diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
> > index f988e9cc2c30..02fc114ffb4f 100644
> > --- a/drivers/soc/qcom/rpmh-rsc.c
> > +++ b/drivers/soc/qcom/rpmh-rsc.c
> > @@ -174,12 +175,13 @@ static void write_tcs_reg(const struct rsc_drv *drv, int reg, int tcs_id,
> > static void write_tcs_reg_sync(const struct rsc_drv *drv, int reg, int tcs_id,
> > u32 data)
> > {
> > + u32 new_data;
> > +
> > writel(data, tcs_reg_addr(drv, reg, tcs_id));
> > - for (;;) {
> > - if (data == readl(tcs_reg_addr(drv, reg, tcs_id)))
> > - break;
> > - udelay(1);
> > - }
> > + if (readl_poll_timeout_atomic(tcs_reg_addr(drv, reg, tcs_id), new_data,
> > + new_data == data, 1, USEC_PER_SEC))
> > + pr_err("%s: error writing %#x to %d:%d\n", drv->name,
>
> Shouldn't the register be hex? That seems to be how the registers are
> represented. But I guess tcs_id is decimal and can't be translated to be
> meaningful enough to indicate which TCS it is like the sleep or wake
> one.
Good point. Should I quickly spin a v3 just so this is all ready to
go, or wait to see if there is any additional feedback?
-Doug
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