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Date:   Thu, 16 Apr 2020 10:26:36 -0500
From:   Dave Kleikamp <dave.kleikamp@...cle.com>
To:     Giovanni Gherdovich <ggherdovich@...e.cz>,
        Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Borislav Petkov <bp@...e.de>, Len Brown <lenb@...nel.org>,
        "Rafael J . Wysocki" <rjw@...ysocki.net>
Cc:     x86@...nel.org, linux-pm@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Mel Gorman <mgorman@...hsingularity.net>,
        Doug Smythies <dsmythies@...us.net>,
        Like Xu <like.xu@...ux.intel.com>,
        Neil Rickert <nwr10cst-oslnx@...oo.com>,
        Chris Wilson <chris@...is-wilson.co.uk>
Subject: Re: [PATCH 2/4] x86, sched: Account for CPUs with less than 4 cores
 in freq. invariance

On 4/16/20 12:47 AM, Giovanni Gherdovich wrote:
> If a CPU has less than 4 physical cores, MSR_TURBO_RATIO_LIMIT will
> rightfully report that the 4C turbo ratio is zero. In such cases, use the
> 1C turbo ratio instead for frequency invariance calculations.

Thank you! This makes my Lenovo T410 happy again. I had tracked down the
problem and come up with a similar patch. I was about to report it when
I came across this patch set.

> 
> Reported-by: Neil Rickert <nwr10cst-oslnx@...oo.com>
> Reported-by: Like Xu <like.xu@...ux.intel.com>
> Signed-off-by: Giovanni Gherdovich <ggherdovich@...e.cz>
> Fixes: 1567c3e3467c ("x86, sched: Add support for frequency invariance")

Tested-by: Dave Kleikamp <dave.kleikamp@...cle.com>

> ---
>  arch/x86/kernel/smpboot.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
> index 3a318ec9bc17..5d346b70844b 100644
> --- a/arch/x86/kernel/smpboot.c
> +++ b/arch/x86/kernel/smpboot.c
> @@ -1945,18 +1945,23 @@ static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size)
>  
>  static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
>  {
> +	u64 msr;
>  	int err;
>  
>  	err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
>  	if (err)
>  		return false;
>  
> -	err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, turbo_freq);
> +	err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
>  	if (err)
>  		return false;
>  
> -	*base_freq = (*base_freq >> 8) & 0xFF;      /* max P state */
> -	*turbo_freq = (*turbo_freq >> 24) & 0xFF;   /* 4C turbo    */
> +	*base_freq = (*base_freq >> 8) & 0xFF;    /* max P state */
> +	*turbo_freq = (msr >> 24) & 0xFF;         /* 4C turbo    */
> +
> +	/* The CPU may have less than 4 cores */
> +	if (!*turbo_freq)
> +		*turbo_freq = msr & 0xFF;         /* 1C turbo    */
>  
>  	return true;
>  }
> 

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