linux-kernel - Re: [PATCH 3/7] mmc: sdhci: fix SDHCI_QUIRK2_CLOCK_DIV_ZERO

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Message-ID: <a49b6a25-14f5-ca1b-b493-e40ec4984b04@intel.com>
Date:   Thu, 16 Apr 2020 10:40:32 +0300
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Michał Mirosław <mirq-linux@...e.qmqm.pl>
Cc:     Suneel Garapati <suneel.garapati@...inx.com>,
        Kevin Liu <kliu5@...vell.com>,
        Michal Simek <michal.simek@...inx.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        linux-kernel@...r.kernel.org, linux-mmc@...r.kernel.org
Subject: Re: [PATCH 3/7] mmc: sdhci: fix SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN

On 15/04/20 7:03 pm, Michał Mirosław wrote:
> On Wed, Apr 15, 2020 at 04:06:02PM +0300, Adrian Hunter wrote:
>> On 2/04/20 2:54 pm, Michał Mirosław wrote:
>>> Fix returned clock rate for SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN case.
>>
>> Does this change anything, because it looks the same to me?
> 
> The value of real_div is fixed this way. With previous code after
> applying the quirk you would have real_div = 1 instead of real_div = 2.

That kind of thing should be in the commit message.  Please also explain
what effect this has (the actual clock value will be too high, but also what
problems does that manifest) and what hardware is affected.

> 
> Best Regards,
> Michał Mirosław
> 
>>
>>>
>>> Signed-off-by: Michał Mirosław <mirq-linux@...e.qmqm.pl>
>>> Cc: stable@...nel.vger.org
>>> Fixes: d1955c3a9a1d ("mmc: sdhci: add quirk SDHCI_QUIRK_CLOCK_DIV_ZERO_BROKEN")
>>> ---
>>>  drivers/mmc/host/sdhci.c | 10 +++++-----
>>>  1 file changed, 5 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
>>> index b2dc4f1cfa5c..a043bf5e3565 100644
>>> --- a/drivers/mmc/host/sdhci.c
>>> +++ b/drivers/mmc/host/sdhci.c
>>> @@ -1807,9 +1807,12 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>>>  
>>>  		if (!host->clk_mul || switch_base_clk) {
>>>  			/* Version 3.00 divisors must be a multiple of 2. */
>>> -			if (host->max_clk <= clock)
>>> +			if (host->max_clk <= clock) {
>>>  				div = 1;
>>> -			else {
>>> +				if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
>>> +					&& host->max_clk <= 25000000)
>>> +					div = 2;
>>> +			} else {
>>>  				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
>>>  				     div += 2) {
>>>  					if ((host->max_clk / div) <= clock)
>>> @@ -1818,9 +1821,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>>>  			}
>>>  			real_div = div;
>>>  			div >>= 1;
>>> -			if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
>>> -				&& !div && host->max_clk <= 25000000)
>>> -				div = 1;
>>>  		}
>>>  	} else {
>>>  		/* Version 2.00 divisors must be a power of 2. */
>>>
>>