linux-kernel - Re: [PATCH v1 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC

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Message-ID: <20200416144036.3ce8432f@collabora.com>
Date:   Thu, 16 Apr 2020 14:40:36 +0200
From:   Boris Brezillon <boris.brezillon@...labora.com>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@...ux.intel.com>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Anders Roxell <anders.roxell@...aro.org>,
        Andriy Shevchenko <andriy.shevchenko@...el.com>,
        Arnd Bergmann <arnd@...db.de>,
        Brendan Higgins <brendanhiggins@...gle.com>,
        cheol.yong.kim@...el.com, devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        "open list:MEMORY TECHNOLOGY..." <linux-mtd@...ts.infradead.org>,
        masonccyang@...c.com.tw, Miquel Raynal <miquel.raynal@...tlin.com>,
        piotrs@...ence.com, qi-ming.wu@...el.com,
        Richard Weinberger <richard@....at>,
        Rob Herring <robh+dt@...nel.org>, Vignesh R <vigneshr@...com>
Subject: Re: [PATCH v1 2/2] mtd: rawnand: Add NAND controller support on
 Intel LGM SoC

On Thu, 16 Apr 2020 15:26:51 +0300
Andy Shevchenko <andy.shevchenko@...il.com> wrote:

> On Thu, Apr 16, 2020 at 3:03 PM Boris Brezillon
> <boris.brezillon@...labora.com> wrote:
> > On Thu, 16 Apr 2020 19:38:03 +0800
> > "Ramuthevar, Vadivel MuruganX"
> > <vadivel.muruganx.ramuthevar@...ux.intel.com> wrote:  
> > > On 16/4/2020 7:17 pm, Boris Brezillon wrote:  
> > > > On Thu, 16 Apr 2020 18:40:53 +0800
> > > > "Ramuthevar, Vadivel MuruganX"
> > > > <vadivel.muruganx.ramuthevar@...ux.intel.com> wrote:  
> 
> ...
> 
> > > There are different features involved and lines of code is more, if we
> > > add new driver patches over xway-nand driver  
> >
> > How about retro-fitting the xway logic into your driver then? I mean,
> > adding a 100 lines of code to your driver to get rid of the 500+ lines
> > we have in xway_nand.c is still a win.
> >  
> > >
> > > is completely looks ugly and it may disturb the existing functionality
> > > as well since we don't have platform to validate:'(.  
> >
> > How ugly? Can you show us? Maybe we can come with a solution to make it
> > less ugly.
> >
> > As for the testing part, there are 4 scenarios:
> >
> > 1/ Your changes work perfectly fine on older platforms. Yay \o/!
> > 2/ You break the xway driver and existing users notice it before this
> >    series gets merged. Now you found someone to validate your changes.
> > 3/ You break the xway driver and none of the existing users notice it
> >    before the driver is merged, but they notice it afterwards. Too bad
> >    this happened after we've merged the driver, but now you've found
> >    someone to help you fix the problem :P.
> > 4/ You break things for old platforms but no one ever complains about
> >    it, either because there's no users left or because they never
> >    update their kernels. In any case, that's no longer your problem.
> >    Someone will remove those old platforms one day and get rid of the
> >    unneeded code in the NAND driver.
> >
> > What's more likely to happen is #3 or #4, and I think the NAND
> > maintainer would be fine with both.
> >
> > Note that the NAND subsystem is full of unmaintained legacy drivers, so
> > every time we see someone who could help us get rid or update one of
> > them we have to take this opportunity.  
> 
> Don't we rather insist to have a MAINTAINERS record for new code to
> avoid (or delay at least) the fate of the legacy drivers?
> 

Well, that's what we do for new drivers, but the xway driver has been
added in 2012 and the policy was not enforced at that time. BTW, that
goes for most of the legacy drivers in have in the NAND subsystems
(some of them even predate the git era).

To be clear, I just checked and there's no official maintainer for this
driver. Best option would be to Cc the original author and contributors
who proposed functional changes to the code, as well as the MIPS
maintainers (Xway is a MIPS platform).