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Message-ID: <AM6PR04MB4966B828D06FCF3C42C5AB8D80AE0@AM6PR04MB4966.eurprd04.prod.outlook.com>
Date: Sun, 26 Apr 2020 04:29:03 +0000
From: Aisheng Dong <aisheng.dong@....com>
To: Peng Fan <peng.fan@....com>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
Leonard Crestez <leonard.crestez@....com>,
"sboyd@...nel.org" <sboyd@...nel.org>,
Abel Vesa <abel.vesa@....com>
CC: "kernel@...gutronix.de" <kernel@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>,
dl-linux-imx <linux-imx@....com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Anson Huang <anson.huang@....com>,
Daniel Baluta <daniel.baluta@....com>,
"aford173@...il.com" <aford173@...il.com>,
Jacky Bai <ping.bai@....com>, Jun Li <jun.li@....com>,
"l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"andrew.smirnov@...il.com" <andrew.smirnov@...il.com>,
"agx@...xcpu.org" <agx@...xcpu.org>,
"angus@...ea.ca" <angus@...ea.ca>,
"heiko@...ech.de" <heiko@...ech.de>,
Andy Duan <fugang.duan@....com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: RE: [PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed
dividers
> From: Peng Fan <peng.fan@....com>
> Sent: Thursday, March 12, 2020 6:20 PM
>
> Inspried from
> commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")
>
> On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each
> with their own gate. Only one of these gates (the one "dividing" by
> one) is currently defined and it's incorrectly set as the parent of all the
> fixed-factor dividers.
>
> Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed
> dividers.
>
> Signed-off-by: Peng Fan <peng.fan@....com>
Reviewed-by: Dong Aisheng <aisheng.dong@....com>
Regards
Aisheng
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