linux-kernel - RE: [PATCH V2 03/10] clk: imx: imx8mp: fix pll mux bit

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <AM6PR04MB496606675B8D3D5C8CE8995780AE0@AM6PR04MB4966.eurprd04.prod.outlook.com>
Date:   Sun, 26 Apr 2020 04:23:13 +0000
From:   Aisheng Dong <aisheng.dong@....com>
To:     Peng Fan <peng.fan@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        Leonard Crestez <leonard.crestez@....com>,
        "sboyd@...nel.org" <sboyd@...nel.org>,
        Abel Vesa <abel.vesa@....com>
CC:     "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        dl-linux-imx <linux-imx@....com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Anson Huang <anson.huang@....com>,
        Daniel Baluta <daniel.baluta@....com>,
        "aford173@...il.com" <aford173@...il.com>,
        Jacky Bai <ping.bai@....com>, Jun Li <jun.li@....com>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        "andrew.smirnov@...il.com" <andrew.smirnov@...il.com>,
        "agx@...xcpu.org" <agx@...xcpu.org>,
        "angus@...ea.ca" <angus@...ea.ca>,
        "heiko@...ech.de" <heiko@...ech.de>,
        Andy Duan <fugang.duan@....com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: RE: [PATCH V2 03/10] clk: imx: imx8mp: fix pll mux bit

> From: Peng Fan <peng.fan@....com>
> Sent: Thursday, March 12, 2020 6:20 PM
> 
> Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll driver for
> glitchless freq setting following spec. If exposing the bit, that means pll driver
> and clk driver has two paths to touch this bit, which is wrong.
> 
> So use EXT_BYPASS bit here.
> 
> Signed-off-by: Peng Fan <peng.fan@....com>

Reviewed-by: Dong Aisheng <aisheng.dong@....com>

Regards
Aisheng