| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <72e8618b-856e-de42-9282-958cd03b239f@kontron.de>
Date: Thu, 30 Apr 2020 15:35:46 +0000
From: Schrempf Frieder <frieder.schrempf@...tron.de>
To: Lucas Stach <l.stach@...gutronix.de>,
Adam Ford <aford173@...il.com>,
Anson Huang <Anson.Huang@....com>,
Christian Gmeiner <christian.gmeiner@...il.com>,
Daniel Baluta <daniel.baluta@....com>,
"Fabio Estevam" <festevam@...il.com>,
Leonard Crestez <leonard.crestez@....com>,
"Li Jun" <jun.li@....com>, NXP Linux Team <linux-imx@....com>,
Peng Fan <peng.fan@....com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
"Russell King" <linux+etnaviv@...linux.org.uk>,
Sascha Hauer <s.hauer@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>,
"S.j. Wang" <shengjiu.wang@....com>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"etnaviv@...ts.freedesktop.org" <etnaviv@...ts.freedesktop.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH 3/4] drm/etnaviv: Change order of enabling clocks to
fix boot on i.MX8MM
On 30.04.20 16:35, Lucas Stach wrote:
> Am Donnerstag, den 30.04.2020, 12:46 +0000 schrieb Schrempf Frieder:
>> From: Frieder Schrempf <frieder.schrempf@...tron.de>
>>
>> On some i.MX8MM devices the boot hangs when enabling the GPU clocks.
>> Changing the order of clock initalization to
>>
>> core -> shader -> bus -> reg
>>
>> fixes the issue. This is the same order used in the imx platform code
>> of the downstream GPU driver in the NXP kernel [1]. For the sake of
>> consistency we also adjust the order of disabling the clocks to the
>> reverse.
>>
>> [1] https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsource.codeaurora.org%2Fexternal%2Fimx%2Flinux-imx%2Ftree%2Fdrivers%2Fmxc%2Fgpu-viv%2Fhal%2Fos%2Flinux%2Fkernel%2Fplatform%2Ffreescale%2Fgc_hal_kernel_platform_imx.c%3Fh%3Dimx_5.4.3_2.0.0%23n1538&data=02%7C01%7Cfrieder.schrempf%40kontron.de%7Cdae15f14ed4a4999065508d7ed13ae87%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637238541095594019&sdata=%2BImteXNH%2FqJDionnJVHtjVnXJk%2BG%2BVlgvBdRGfnlQro%3D&reserved=0
>
> I don't see why the order of the clocks is important. Is this really a
> GPU issue? As in: does a GPU access hang when enabling the clocks in
> the wrong order? Or is this a clock driver issue with a clock access
> hanging due to an upstream clock still being disabled?
Actually you might be right with this being a clock driver issue. The
hanging happens while enabling the clocks (unrelated to any GPU register
access). The strange thing is that most of the devices we have don't
care and work as is and some devices reliably fail each time when
enabling the clocks in the "wrong" order.
So I guess this could indeed be some clock being enabled with an
upstream PLL not having locked yet or something.
>
> Regards,
> Lucas
>
>> Signed-off-by: Frieder Schrempf <frieder.schrempf@...tron.de>
>> ---
>> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 42 +++++++++++++--------------
>> 1 file changed, 21 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>> index 7b138d4dd068..424b2e5951f0 100644
>> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
>> @@ -1487,55 +1487,55 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
>> {
>> int ret;
>>
>> - if (gpu->clk_reg) {
>> - ret = clk_prepare_enable(gpu->clk_reg);
>> + if (gpu->clk_core) {
>> + ret = clk_prepare_enable(gpu->clk_core);
>> if (ret)
>> return ret;
>> }
>>
>> - if (gpu->clk_bus) {
>> - ret = clk_prepare_enable(gpu->clk_bus);
>> + if (gpu->clk_shader) {
>> + ret = clk_prepare_enable(gpu->clk_shader);
>> if (ret)
>> - goto disable_clk_reg;
>> + goto disable_clk_core;
>> }
>>
>> - if (gpu->clk_core) {
>> - ret = clk_prepare_enable(gpu->clk_core);
>> + if (gpu->clk_bus) {
>> + ret = clk_prepare_enable(gpu->clk_bus);
>> if (ret)
>> - goto disable_clk_bus;
>> + goto disable_clk_shader;
>> }
>>
>> - if (gpu->clk_shader) {
>> - ret = clk_prepare_enable(gpu->clk_shader);
>> + if (gpu->clk_reg) {
>> + ret = clk_prepare_enable(gpu->clk_reg);
>> if (ret)
>> - goto disable_clk_core;
>> + goto disable_clk_bus;
>> }
>>
>> return 0;
>>
>> -disable_clk_core:
>> - if (gpu->clk_core)
>> - clk_disable_unprepare(gpu->clk_core);
>> disable_clk_bus:
>> if (gpu->clk_bus)
>> clk_disable_unprepare(gpu->clk_bus);
>> -disable_clk_reg:
>> - if (gpu->clk_reg)
>> - clk_disable_unprepare(gpu->clk_reg);
>> +disable_clk_shader:
>> + if (gpu->clk_shader)
>> + clk_disable_unprepare(gpu->clk_shader);
>> +disable_clk_core:
>> + if (gpu->clk_core)
>> + clk_disable_unprepare(gpu->clk_core);
>>
>> return ret;
>> }
>>
>> static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
>> {
>> + if (gpu->clk_reg)
>> + clk_disable_unprepare(gpu->clk_reg);
>> + if (gpu->clk_bus)
>> + clk_disable_unprepare(gpu->clk_bus);
>> if (gpu->clk_shader)
>> clk_disable_unprepare(gpu->clk_shader);
>> if (gpu->clk_core)
>> clk_disable_unprepare(gpu->clk_core);
>> - if (gpu->clk_bus)
>> - clk_disable_unprepare(gpu->clk_bus);
>> - if (gpu->clk_reg)
>> - clk_disable_unprepare(gpu->clk_reg);
>>
>> return 0;
>> }
>
Powered by blists - more mailing lists