lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 6 May 2020 16:29:47 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc:     Kai-Heng Feng <kai.heng.feng@...onical.com>, bhelgaas@...gle.com,
        Heiner Kallweit <hkallweit1@...il.com>,
        "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
        Keith Busch <keith.busch@...el.com>,
        Chris Packham <chris.packham@...iedtelesis.co.nz>,
        Yicong Yang <yangyicong@...ilicon.com>,
        Krzysztof Wilczynski <kw@...ux.com>,
        "open list:PCI SUBSYSTEM" <linux-pci@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link

On Wed, May 06, 2020 at 09:14:38AM +0300, Mika Westerberg wrote:
> On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote:
> > The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power
> > state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary
> > power. On Windows ASPM L1 is enabled on the device and its upstream
> > bridge, so it can make the Intel SoC reach PC8 or PC10 to save lots of
> > power.
> > 
> > In short, ASPM always gets disabled on bridge-to-bridge link.
> 
> Excelent finding :) I've heard several reports complaining that we can't
> enter PC10 when TBT is enabled and I guess this explains it.

I'm curious about this.  I first read this patch as affecting
garden-variety Links between a Root Port or Downstream Port and the
Upstream Port of a switch.  But the case we're talking about is
specifically when the downstream device is PCI_EXP_TYPE_PCI_BRIDGE,
i.e., a PCIe to PCI/PCI-X bridge, not a switch.

AFAICT, a Link to a PCI bridge is still a normal Link and ASPM should
still work.  I'm sort of surprised that you'd find such a PCIe to
PCI/PCI-X bridge in a Thunderbolt topology, but maybe that's a common
thing?

I guess "PC8" and "PC10" are some sort of Intel-specific power states?

> > The special case was part of first ASPM introduction patch, commit
> > 7d715a6c1ae5 ("PCI: add PCI Express ASPM support"). However, it didn't
> > explain why ASPM needs to be disabled in special bridge-to-bridge case.
> > 
> > Let's remove the the special case, as PCIe spec already envisioned ASPM
> > on bridge-to-bridge link.
> > 
> > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=207571
> > Signed-off-by: Kai-Heng Feng <kai.heng.feng@...onical.com>
> 
> Reviewed-by: Mika Westerberg <mika.westerberg@...ux.intel.com>

Powered by blists - more mailing lists