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Date:   Wed, 6 May 2020 09:14:38 +0300
From:   Mika Westerberg <>
To:     Kai-Heng Feng <>
Cc:, Heiner Kallweit <>,
        "Rafael J. Wysocki" <>,
        Keith Busch <>,
        Chris Packham <>,
        Yicong Yang <>,
        Krzysztof Wilczynski <>,
        "open list:PCI SUBSYSTEM" <>,
        open list <>
Subject: Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link

On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote:
> The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power
> state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary
> power. On Windows ASPM L1 is enabled on the device and its upstream
> bridge, so it can make the Intel SoC reach PC8 or PC10 to save lots of
> power.
> In short, ASPM always gets disabled on bridge-to-bridge link.

Excelent finding :) I've heard several reports complaining that we can't
enter PC10 when TBT is enabled and I guess this explains it.

> The special case was part of first ASPM introduction patch, commit
> 7d715a6c1ae5 ("PCI: add PCI Express ASPM support"). However, it didn't
> explain why ASPM needs to be disabled in special bridge-to-bridge case.
> Let's remove the the special case, as PCIe spec already envisioned ASPM
> on bridge-to-bridge link.
> Bugzilla:
> Signed-off-by: Kai-Heng Feng <>

Reviewed-by: Mika Westerberg <>

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