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Date:   Wed, 6 May 2020 12:03:03 +0530
From:   Anshuman Khandual <anshuman.khandual@....com>
To:     Suzuki K Poulose <suzuki.poulose@....com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     catalin.marinas@....com, will@...nel.org, mark.rutland@....com,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in
 ID_AA64PFR1 register



On 05/05/2020 02:54 PM, Suzuki K Poulose wrote:
> On 05/02/2020 02:34 PM, Anshuman Khandual wrote:
>> Enable the following features bits in ID_AA64PFR1 register as per ARM DDI
>> 0487F.a specification.
>>
>> Cc: Catalin Marinas <catalin.marinas@....com>
>> Cc: Will Deacon <will@...nel.org>
>> Cc: Mark Rutland <mark.rutland@....com>
>> Cc: Suzuki K Poulose <suzuki.poulose@....com>
>> Cc: linux-arm-kernel@...ts.infradead.org
>> Cc: linux-kernel@...r.kernel.org
>>
>> Suggested-by: Will Deacon <will@...nel.org>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>
>> ---
>>   arch/arm64/include/asm/sysreg.h | 4 ++++
>>   arch/arm64/kernel/cpufeature.c  | 4 ++++
>>   2 files changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index c93ea6613f51..f1c0d874220a 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -666,7 +666,11 @@
>>   #define ID_AA64PFR0_EL0_32BIT_64BIT    0x2
>>     /* id_aa64pfr1 */
>> +#define ID_AA64PFR1_MPAMFRAC_SHIFT    16
>> +#define ID_AA64PFR1_RASFRAC_SHIFT    12
>> +#define ID_AA64PFR1_MTE_SHIFT        8
>>   #define ID_AA64PFR1_SSBS_SHIFT        4
>> +#define ID_AA64PFR1_BT_SHIFT        0
>>     #define ID_AA64PFR1_SSBS_PSTATE_NI    0
>>   #define ID_AA64PFR1_SSBS_PSTATE_ONLY    1
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index f5a39e040804..181e09d62147 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -233,7 +233,11 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
>>   };
>>     static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
>> +    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
>> +    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
> 
> These should be hidden as well.

Will change.

> 
>> +    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, 0),
>>       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
>> +    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
> 
> I would say remove the MTE, BTI fields for now. As they must be VISIBLE, but with the kernel support for these merged. They will be added with their respective series.
Sure, will drop above changes from the series.

> 
> Suzuki
> 

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