linux-kernel - Re: [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in ID

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Message-ID: <7116fd7d-eb16-c5c4-c8e4-ffdc71b0983c@arm.com>
Date:   Wed, 6 May 2020 12:05:50 +0530
From:   Anshuman Khandual <anshuman.khandual@....com>
To:     Suzuki K Poulose <suzuki.poulose@....com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     catalin.marinas@....com, will@...nel.org, mark.rutland@....com,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in
 ID_AA64PFR0 register



On 05/05/2020 10:29 AM, Suzuki K Poulose wrote:
> On 05/02/2020 02:33 PM, Anshuman Khandual wrote:
>> Enable MPAM and SEL2 features bits in ID_AA64PFR0 register as per ARM DDI
>> 0487F.a specification.
>>
>> Cc: Catalin Marinas <catalin.marinas@....com>
>> Cc: Will Deacon <will@...nel.org>
>> Cc: Mark Rutland <mark.rutland@....com>
>> Cc: Suzuki K Poulose <suzuki.poulose@....com>
>> Cc: linux-arm-kernel@...ts.infradead.org
>> Cc: linux-kernel@...r.kernel.org
>>
>> Suggested-by: Will Deacon <will@...nel.org>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>
>> ---
>>   arch/arm64/include/asm/sysreg.h | 2 ++
>>   arch/arm64/kernel/cpufeature.c  | 2 ++
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 40eaf89f1032..c93ea6613f51 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -641,6 +641,8 @@
>>   #define ID_AA64PFR0_CSV2_SHIFT        56
>>   #define ID_AA64PFR0_DIT_SHIFT        48
>>   #define ID_AA64PFR0_AMU_SHIFT        44
>> +#define ID_AA64PFR0_MPAM_SHIFT        40
>> +#define ID_AA64PFR0_SEL2_SHIFT        36
>>   #define ID_AA64PFR0_SVE_SHIFT        32
>>   #define ID_AA64PFR0_RAS_SHIFT        28
>>   #define ID_AA64PFR0_GIC_SHIFT        24
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index dbedcae28061..f5a39e040804 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -217,6 +217,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
>>       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
>> +    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
>> +    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
> 
> Both of them must be hidden. And also need to check the impact of exposing this to the guests, especially MPAM.

Just trying to understand. We should make both MPAM and SEL2, FTR_HIDDEN for
now, in which case they should not be visible to the userspace or guests. But
we would need to check impact of their exposure to guests before they can be
made visible later on. Is that correct ?