linux-kernel - Re: [PATCH v7 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver

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Message-ID: <20200507194939.GA21050@bjorn-Precision-5520>
Date:   Thu, 7 May 2020 14:49:39 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
Cc:     linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        lorenzo.pieralisi@....com, bhelgaas@...gle.com, robh@...nel.org,
        rgummal@...inx.com
Subject: Re: [PATCH v7 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver

On Thu, May 07, 2020 at 05:28:36PM +0530, Bharat Kumar Gogada wrote:
> - Add support for Versal CPM as Root Port.
> - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
>   block for CPM along with the integrated bridge can function
>   as PCIe Root Port.
> - Bridge error and legacy interrupts in Versal CPM are handled using
>   Versal CPM specific interrupt line.

> +static inline bool cpm_pcie_link_up(struct xilinx_cpm_pcie_port *port)
> +{
> +	return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) &
> +		XILINX_CPM_PCIE_REG_PSCR_LNKUP) ? 1 : 0;

Almost all of the *_link_up() functions return "int".  I don't know if
there's really any benefit to using "bool", but if you do, you should
probably return "true" or "false" instead of 1/0.

> +	port->irq_misc = platform_get_irq(pdev, 0);
> +	if (port->irq_misc <= 0) {

Use:

  if (port->irq_misc < 0) {

See https://lore.kernel.org/r/20200501224042.141366-3-helgaas@kernel.org