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Message-ID: <20200508102210.GC4820@sirena.org.uk>
Date: Fri, 8 May 2020 11:22:10 +0100
From: Mark Brown <broonie@...nel.org>
To: Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc: Andy Shevchenko <andy.shevchenko@...il.com>,
Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>,
Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Paul Burton <paulburton@...nel.org>,
Ralf Baechle <ralf@...ux-mips.org>,
Lee Jones <lee.jones@...aro.org>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Arnd Bergmann <arnd@...db.de>,
Rob Herring <robh+dt@...nel.org>, linux-mips@...r.kernel.org,
devicetree <devicetree@...r.kernel.org>,
John Garry <john.garry@...wei.com>,
Chuanhong Guo <gch981213@...il.com>,
Eddie James <eajames@...ux.ibm.com>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
Chris Packham <chris.packham@...iedtelesis.co.nz>,
Tomer Maimon <tmaimon77@...il.com>,
Masahisa Kojima <masahisa.kojima@...aro.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Florian Fainelli <f.fainelli@...il.com>,
Jassi Brar <jaswinder.singh@...aro.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-spi <linux-spi@...r.kernel.org>
Subject: Re: [PATCH 2/2] spi: Add Baikal-T1 System Boot SPI Controller driver
On Fri, May 08, 2020 at 01:15:41PM +0300, Serge Semin wrote:
> On Fri, May 08, 2020 at 01:03:11PM +0300, Andy Shevchenko wrote:
> > > slave device. Taking into account the peculiarities of the controller
> > > registers and physically mapped SPI flash access, very limited resources
> > > and seeing the normal usecase of the controller is to access an external
> > > SPI-nor flash, we decided to create a dedicated SPI driver for it.
> > It seems a lot of code.
> > Why can't you use spi-dw-mmio.c et al.?
> I said above why. Even though the registers set is similar It's too specific
> to be integrated into the generic DW SSI driver.
Can you be more specific about the issues? From what you wrote it
sounded like the main thing was chip select handling.
> > > The driver provides callbacks for native messages-based SPI interface,
> > > SPI-memory and direct mapping read operations. Due to not having any
> > > asynchronous signaling interface provided by the core we have no choice
What do you mean by "asynchronous signaling interface provided by the
core" here?
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