lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20200512164233.GB12151@bogus>
Date:   Tue, 12 May 2020 11:42:33 -0500
From:   Rob Herring <robh@...nel.org>
To:     Jiaxun Yang <jiaxun.yang@...goat.com>
Cc:     maz@...nel.org, Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Huacai Chen <chenhc@...ote.com>, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-mips@...r.kernel.org
Subject: Re: [PATCH v3 2/6] dt-bindings: interrupt-controller: Add Loongson
 HTVEC

On Fri, May 01, 2020 at 05:21:33PM +0800, Jiaxun Yang wrote:
> Add binding for Loongson-3 HyperTransport Interrupt Vector Controller.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
> ---
>  .../interrupt-controller/loongson,htvec.yaml  | 59 +++++++++++++++++++
>  1 file changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml
> new file mode 100644
> index 000000000000..547a80c89eba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Loongson-3 HyperTransport Interrupt Vector Controller
> +
> +maintainers:
> +  - Jiaxun Yang <jiaxun.yang@...goat.com>
> +
> +allOf:
> +  - $ref: /schemas/interrupt-controller.yaml#

Don't need this. It's already applied to any node named 
'interrupt-controller'.

> +
> +description: |

Can drop '|' if you don't need formatting.

> +  This interrupt controller is found in the Loongson-3 family of chips for
> +  receiving vectorized interrupts from PCH's interrupt controller.
> +
> +properties:
> +  compatible:
> +    const: loongson,htvec-1.0
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 4
> +    description: |
> +      Four parent interrupts that receive chained interrupts.
> +
> +  interrupt-controller: true
> +
> +  '#interrupt-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-controller
> +  - '#interrupt-cells'

Add:

additionalProperties: false

> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    htvec: interrupt-controller@...000080 {

Unit-address doesn't match reg.

> +      compatible = "loongson,htvec-1.0";
> +      reg = <0xfb000080 0x40>;
> +      interrupt-controller;
> +      #interrupt-cells = <1>;
> +
> +      interrupt-parent = <&liointc>;
> +      interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> +                    <25 IRQ_TYPE_LEVEL_HIGH>,
> +                    <26 IRQ_TYPE_LEVEL_HIGH>,
> +                    <27 IRQ_TYPE_LEVEL_HIGH>;
> +    };
> +...
> -- 
> 2.26.0.rc2
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ