linux-kernel - Re: R: [PATCH v3 09/11] PCI: qcom: add ipq8064 rev2 variant and set tx term offset

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Message-ID: <37ddf6ac-43c8-f2f1-ce53-e0959084b77c@mm-sol.com>
Date:   Wed, 13 May 2020 16:49:10 +0300
From:   Stanimir Varbanov <svarbanov@...sol.com>
To:     ansuelsmth@...il.com,
        'Bjorn Andersson' <bjorn.andersson@...aro.org>
Cc:     'Sham Muthayyan' <smuthayy@...eaurora.org>,
        'Andy Gross' <agross@...nel.org>,
        'Bjorn Helgaas' <bhelgaas@...gle.com>,
        'Rob Herring' <robh+dt@...nel.org>,
        'Mark Rutland' <mark.rutland@....com>,
        'Lorenzo Pieralisi' <lorenzo.pieralisi@....com>,
        'Andrew Murray' <amurray@...goodpenguin.co.uk>,
        'Philipp Zabel' <p.zabel@...gutronix.de>,
        linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: R: [PATCH v3 09/11] PCI: qcom: add ipq8064 rev2 variant and set
 tx term offset



On 5/13/20 3:54 PM, ansuelsmth@...il.com wrote:
>> Hi Ansuel,
>>
>> On 5/1/20 1:06 AM, Ansuel Smith wrote:
>>> From: Sham Muthayyan <smuthayy@...eaurora.org>
>>>
>>> Add tx term offset support to pcie qcom driver need in some revision of
>>> the ipq806x SoC.
>>> Ipq8064 have tx term offset set to 7.
>>> Ipq8064-v2 revision and ipq8065 have the tx term offset set to 0.
>>>
>>> Signed-off-by: Sham Muthayyan <smuthayy@...eaurora.org>
>>> Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
>>> ---
>>>  drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++++
>>>  1 file changed, 15 insertions(+)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
>> b/drivers/pci/controller/dwc/pcie-qcom.c
>>> index da8058fd1925..372d2c8508b5 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>> @@ -45,6 +45,9 @@
>>>  #define PCIE_CAP_CPL_TIMEOUT_DISABLE		0x10
>>>
>>>  #define PCIE20_PARF_PHY_CTRL			0x40
>>> +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK	GENMASK(12,
>> 16)
>>
>> The mask definition is not correct. Should be GENMASK(20, 16)
>>
>>> +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)		((x) << 16)
>>> +
>>>  #define PCIE20_PARF_PHY_REFCLK			0x4C
>>>  #define PHY_REFCLK_SSP_EN			BIT(16)
>>>  #define PHY_REFCLK_USE_PAD			BIT(12)
>>> @@ -118,6 +121,7 @@ struct qcom_pcie_resources_2_1_0 {
>>>  	u32 tx_swing_full;
>>>  	u32 tx_swing_low;
>>>  	u32 rx0_eq;
>>> +	u8 phy_tx0_term_offset;
>>>  };
>>>
>>>  struct qcom_pcie_resources_1_0_0 {
>>> @@ -318,6 +322,11 @@ static int
>> qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
>>>  	if (IS_ERR(res->ext_reset))
>>>  		return PTR_ERR(res->ext_reset);
>>>
>>> +	if (of_device_is_compatible(dev->of_node, "qcom,pcie-ipq8064"))
>>> +		res->phy_tx0_term_offset = 7;
>>
>> Before your change the phy_tx0_term_offser was 0 for apq8064, but here
>> you change it to 7, why?
>>
> 
> apq8064 board should use qcom,pcie-apq8064 right? This should be set to 0
> only with pcie-ipq8064 compatible. Tell me if I'm wrong.

Sorry, my fault. I read the compatible check above as apq8064 but it is ipq.

-- 
regards,
Stan