[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <871rno3uab.fsf@nanos.tec.linutronix.de>
Date: Wed, 13 May 2020 14:15:40 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Jiaxun Yang <jiaxun.yang@...goat.com>, maz@...nel.org
Cc: Jiaxun Yang <jiaxun.yang@...goat.com>,
Jason Cooper <jason@...edaemon.net>,
Rob Herring <robh+dt@...nel.org>,
Huacai Chen <chenhc@...ote.com>, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-mips@...r.kernel.org
Subject: Re: [PATCH v2 5/6] irqchip: Add Loongson PCH MSI controller
Thomas Gleixner <tglx@...utronix.de> writes:
> Jiaxun Yang <jiaxun.yang@...goat.com> writes:
>> +
>> +struct pch_msi_data {
>> + spinlock_t msi_map_lock;
>> + phys_addr_t doorbell;
>> + u32 irq_first; /* The vector number that MSIs starts */
>> + u32 num_irqs; /* The number of vectors for MSIs */
>> + unsigned long *msi_map;
>> +};
>> +
>> +static void pch_msi_mask_msi_irq(struct irq_data *d)
>> +{
>> + pci_msi_mask_irq(d);
>> + irq_chip_mask_parent(d);
>> +}
>> +
>> +static void pch_msi_unmask_msi_irq(struct irq_data *d)
>> +{
>> + pci_msi_unmask_irq(d);
>> + irq_chip_unmask_parent(d);
>
> The ordering of mask and unmask is assymetric. That does not make sense.
>
>> +static struct msi_domain_info pch_msi_domain_info = {
>> + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
>> + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
>> + .chip = &pch_msi_irq_chip,
>
> Please maintain tabular layout.
Ooops. Wanted to reply to V3, but the comments are valid for V3 as well.
Thanks,
tglx
Powered by blists - more mailing lists