[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20200513130842.24847-6-lars.povlsen@microchip.com>
Date: Wed, 13 May 2020 15:08:42 +0200
From: Lars Povlsen <lars.povlsen@...rochip.com>
To: Sebastian Reichel <sre@...nel.org>, SoC Team <soc@...nel.org>
CC: Lars Povlsen <lars.povlsen@...rochip.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
<linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH 5/5] arm64: dts: sparx5: Add reset support
This adds reset support to the Sparx5 SoC
Signed-off-by: Lars Povlsen <lars.povlsen@...rochip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index b5cb3d8dc876b..3e94ac9e7dd51 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -106,6 +106,17 @@ gic: interrupt-controller@...300000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ cpu_ctrl: syscon@...000000 {
+ compatible = "microchip,sparx5-cpu-syscon", "syscon";
+ reg = <0x6 0x00000000 0xd0>;
+ };
+
+ reset@...010008 {
+ compatible = "microchip,sparx5-chip-reset";
+ reg = <0x6 0x11010008 0x4>;
+ microchip,reset-switch-core;
+ };
+
uart0: serial@...100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
--
2.26.2
Powered by blists - more mailing lists