linux-kernel - Re: [PATCH v2 03/19] spi: dw: Clear DMAC register when done or stopped

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 15 May 2020 15:01:58 +0300
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc:     Mark Brown <broonie@...nel.org>,
        Serge Semin <fancer.lancer@...il.com>,
        Georgy Vlasov <Georgy.Vlasov@...kalelectronics.ru>,
        Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Arnd Bergmann <arnd@...db.de>,
        Allison Randal <allison@...utok.net>,
        Gareth Williams <gareth.williams.jx@...esas.com>,
        Rob Herring <robh+dt@...nel.org>, linux-mips@...r.kernel.org,
        devicetree@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
        Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@...el.com>,
        Jarkko Nikula <jarkko.nikula@...ux.intel.com>,
        linux-spi@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 03/19] spi: dw: Clear DMAC register when done or
 stopped

On Fri, May 15, 2020 at 01:47:42PM +0300, Serge Semin wrote:
> If DMAC register is left uncleared any further DMAless transfers
> may cause the DMAC hardware handshaking interface getting activated.
> So the next DMA-based Rx/Tx transaction will be started right
> after the dma_async_issue_pending() method is invoked even if no
> DMATDLR/DMARDLR conditions are met. This at the same time may cause
> the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
> must clear DMAC register after a current DMA-based transaction is
> finished.

After adding a Fixes tag,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>

> 
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@...kalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@...kalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
> Cc: Paul Burton <paulburton@...nel.org>
> Cc: Ralf Baechle <ralf@...ux-mips.org>
> Cc: Arnd Bergmann <arnd@...db.de>
> Cc: Allison Randal <allison@...utok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@...esas.com>
> Cc: Rob Herring <robh+dt@...nel.org>
> Cc: linux-mips@...r.kernel.org
> Cc: devicetree@...r.kernel.org
> 
> ---
> 
> Changelog v2:
> - Move the patch to the head of the series so one could be picked up to
>   the stable kernels as a fix.
> - Clear the DMACR in the DMA exit callback too.
> ---
>  drivers/spi/spi-dw-mid.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
> index 7a5ae1506365..0c597b6bb154 100644
> --- a/drivers/spi/spi-dw-mid.c
> +++ b/drivers/spi/spi-dw-mid.c
> @@ -108,6 +108,8 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
>  		dmaengine_terminate_sync(dws->rxchan);
>  		dma_release_channel(dws->rxchan);
>  	}
> +
> +	dw_writel(dws, DW_SPI_DMACR, 0);
>  }
>  
>  static irqreturn_t dma_transfer(struct dw_spi *dws)
> @@ -178,6 +180,8 @@ static void dw_spi_dma_tx_done(void *arg)
>  	clear_bit(TX_BUSY, &dws->dma_chan_busy);
>  	if (test_bit(RX_BUSY, &dws->dma_chan_busy))
>  		return;
> +
> +	dw_writel(dws, DW_SPI_DMACR, 0);
>  	spi_finalize_current_transfer(dws->master);
>  }
>  
> @@ -249,6 +253,8 @@ static void dw_spi_dma_rx_done(void *arg)
>  	clear_bit(RX_BUSY, &dws->dma_chan_busy);
>  	if (test_bit(TX_BUSY, &dws->dma_chan_busy))
>  		return;
> +
> +	dw_writel(dws, DW_SPI_DMACR, 0);
>  	spi_finalize_current_transfer(dws->master);
>  }
>  
> @@ -342,6 +348,8 @@ static void mid_spi_dma_stop(struct dw_spi *dws)
>  		dmaengine_terminate_sync(dws->rxchan);
>  		clear_bit(RX_BUSY, &dws->dma_chan_busy);
>  	}
> +
> +	dw_writel(dws, DW_SPI_DMACR, 0);
>  }
>  
>  static const struct dw_spi_dma_ops mfld_dma_ops = {
> -- 
> 2.25.1
> 

-- 
With Best Regards,
Andy Shevchenko