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Date:   Mon, 18 May 2020 03:40:04 +0000
From:   Aisheng Dong <aisheng.dong@....com>
To:     Anson Huang <anson.huang@....com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "jason@...edaemon.net" <jason@...edaemon.net>,
        "maz@...nel.org" <maz@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
CC:     dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH] dt-bindings: interrupt-controller: Convert imx irqsteer
 to json-schema

...
> +
> +title: Freescale IRQSTEER Interrupt multiplexer
> +
> +maintainers:
> +  - Lucas Stach <l.stach@...gutronix.de>
> +
> +properties:
> +  compatible:
> +    const: fsl,imx-irqsteer

You changed binding here without comments?

Regards
Aisheng

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    description: |
> +      should contain the up to 8 parent interrupt lines used to multiplex
> +      the input interrupts. They should be specified sequentially from
> +      output 0 to 7.
> +    items:
> +      - description: irqsteer channel 0
> +      - description: irqsteer channel 1
> +      - description: irqsteer channel 2
> +      - description: irqsteer channel 3
> +      - description: irqsteer channel 4
> +      - description: irqsteer channel 5
> +      - description: irqsteer channel 6
> +      - description: irqsteer channel 7
> +    minItems: 1
> +    maxItems: 8
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: ipg
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 1
> +
> +  fsl,channel:
> +    $ref: '/schemas/types.yaml#/definitions/uint32'
> +    description: |
> +      u32 value representing the output channel that all input IRQs should be
> +      steered into.
> +
> +  fsl,num-irqs:
> +    $ref: '/schemas/types.yaml#/definitions/uint32'
> +    description: |
> +      u32 value representing the number of input interrupts of this channel,
> +      should be multiple of 32 input interrupts and up to 512 interrupts.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +  - fsl,channel
> +  - fsl,num-irqs
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/imx8mq-clock.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    interrupt-controller@...2d000 {
> +        compatible = "fsl,imx-irqsteer";
> +        reg = <0x32e2d000 0x1000>;
> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
> +        clock-names = "ipg";
> +        fsl,channel = <0>;
> +        fsl,num-irqs = <64>;
> +        interrupt-controller;
> +        #interrupt-cells = <1>;
> +    };
> --
> 2.7.4

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