linux-kernel - Re: [PATCH v4 05/13] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs

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Date:   Fri, 22 May 2020 09:28:18 +0200
From:   Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To:     Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc:     Paul Burton <paulburton@...nel.org>,
        Serge Semin <fancer.lancer@...il.com>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Arnd Bergmann <arnd@...db.de>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 05/13] mips: Fix cpu_has_mips64r1/2 activation for
 MIPS32 CPUs

On Thu, May 21, 2020 at 05:07:16PM +0300, Serge Semin wrote:
> Commit 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA
> allows") updated the cpu_has_mips* macro to be replaced with a constant
> expression where it's possible. By mistake it wasn't done correctly
> for cpu_has_mips64r1/cpu_has_mips64r2 macro. They are defined to
> be replaced with conditional expression __isa_range_or_flag(), which
> means either ISA revision being within the range or the corresponding
> CPU options flag was set at the probe stage or both being true at the
> same time. But the ISA level value doesn't indicate whether the ISA is
> MIPS32 or MIPS64. Due to this if we select MIPS32r1 - MIPS32r5
> architectures the __isa_range() macro will activate the
> cpu_has_mips64rX flags, which is incorrect. In order to fix the
> problem we make sure the 64bits CPU support is enabled by means of
> checking the flag cpu_has_64bits aside with proper ISA range and specific
> Revision flag being set.
> 
> Fixes: 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA allows")
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
> Cc: Paul Burton <paulburton@...nel.org>
> Cc: Ralf Baechle <ralf@...ux-mips.org>
> Cc: Arnd Bergmann <arnd@...db.de>
> Cc: Rob Herring <robh+dt@...nel.org>
> Cc: devicetree@...r.kernel.org
> ---
>  arch/mips/include/asm/cpu-features.h | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)

applied to mips-next.

Thomas.

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