linux-kernel - Re: [PATCH v4 06/13] mips: Add CP0 Write Merge config support

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Message-ID: <20200522072837.GD7331@alpha.franken.de>
Date:   Fri, 22 May 2020 09:28:37 +0200
From:   Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To:     Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc:     Serge Semin <fancer.lancer@...il.com>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Arnd Bergmann <arnd@...db.de>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        Philippe Mathieu-Daudé <f4bug@...at.org>,
        Huacai Chen <chenhc@...ote.com>,
        Paul Cercueil <paul@...pouillou.net>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Zhou Yanjie <zhouyanjie@...o.com>,
        WANG Xuerui <git@...0n.name>,
        周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>, YunQiang Su <syq@...ian.org>,
        Liangliang Huang <huanglllzu@...il.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 06/13] mips: Add CP0 Write Merge config support

On Thu, May 21, 2020 at 05:07:17PM +0300, Serge Semin wrote:
> CP0 config register may indicate whether write-through merging
> is allowed. Currently there are two types of the merging available:
> SysAD Valid and Full modes. Whether each of them are supported by
> the core is implementation dependent. Moreover whether the ability
> to change the mode also depends on the chip family instance. Taking
> into account all of this we created a dedicated mm_config() method
> to detect and enable merging if it's supported. It is called for
> MIPS-type processors at CPU-probe stage and attempts to detect whether
> the write merging is available. If it's known to be supported and
> switchable, then switch on the full mode. Otherwise just perform the
> CP0.Config.MM field analysis.
> 
> In addition there are platforms like InterAptiv/ProAptiv, which do have
> the MM bit field set by default, but having write-through cacheing
> unsupported makes write-merging also unsupported. In this case we just
> ignore the MM field value.
> 
> Co-developed-by: Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>
> Signed-off-by: Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
> Cc: Paul Burton <paulburton@...nel.org>
> Cc: Ralf Baechle <ralf@...ux-mips.org>
> Cc: Arnd Bergmann <arnd@...db.de>
> Cc: Rob Herring <robh+dt@...nel.org>
> Cc: devicetree@...r.kernel.org
> ---
>  arch/mips/include/asm/cpu-features.h |  8 +++++
>  arch/mips/include/asm/cpu.h          |  4 ++-
>  arch/mips/include/asm/mipsregs.h     |  3 ++
>  arch/mips/kernel/cpu-probe.c         | 48 ++++++++++++++++++++++++++++
>  4 files changed, 62 insertions(+), 1 deletion(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]