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Message-ID: <20200522155017.GG26492@gaia>
Date: Fri, 22 May 2020 16:50:17 +0100
From: Catalin Marinas <catalin.marinas@....com>
To: Zhenyu Ye <yezhenyu2@...wei.com>
Cc: peterz@...radead.org, mark.rutland@....com, will@...nel.org,
aneesh.kumar@...ux.ibm.com, akpm@...ux-foundation.org,
npiggin@...il.com, arnd@...db.de, rostedt@...dmis.org,
maz@...nel.org, suzuki.poulose@....com, tglx@...utronix.de,
yuzhao@...gle.com, Dave.Martin@....com, steven.price@....com,
broonie@...nel.org, guohanjun@...wei.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arch@...r.kernel.org, linux-mm@...ck.org, arm@...nel.org,
xiexiangyou@...wei.com, prime.zeng@...ilicon.com,
zhangshaokun@...ilicon.com, kuhn.chenqun@...wei.com
Subject: Re: [PATCH v2 2/6] arm64: Add level-hinted TLB invalidation helper
On Thu, Apr 23, 2020 at 09:56:52PM +0800, Zhenyu Ye wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index bc3949064725..5f9f189bc6d2 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -10,6 +10,7 @@
>
> #ifndef __ASSEMBLY__
>
> +#include <linux/bitfield.h>
> #include <linux/mm_types.h>
> #include <linux/sched.h>
> #include <asm/cputype.h>
> @@ -59,6 +60,35 @@
> __ta; \
> })
>
> +#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
> +
> +#define __tlbi_level(op, addr, level) \
> + do { \
Nitpick: move "do {" on the same line as __tlbi_level() to reduce the
indentation levels of the whole block.
Reviewed-by: Catalin Marinas <catalin.marinas@....com>
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