lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 23 May 2020 10:19:52 -0700
From:   Andy Lutomirski <>
To:     Arvind Sankar <>
Cc:     Thomas Gleixner <>,
        Ingo Molnar <>, Borislav Petkov <>,
        "Kirill A. Shutemov" <>,
        Linus Torvalds <>,
        X86 ML <>, LKML <>
Subject: Re: x86: Question about state of general purpose registers on switch
 to 64-bit mode

On Sat, May 23, 2020 at 8:57 AM Arvind Sankar <> wrote:
> Hi,
> I have a question about the state of the upper 32 bits of the general
> purpose registers following a switch from/to 64-bit mode.
> Both the AMD [0] and Intel [1] manuals state that these bits are
> undefined following a switch from 64 to 32-bit mode. Since they can't be
> accessed in 32-bit mode, presumably this means they are undefined once
> you switch back to 64-bit mode and can see them again.

I would guess that all x86_64 CPUs actually preserve those registers
across mode changes and clear the high bits on 32-bit operations.  But
making the kernel boot code more robust sounds entirely sensible to

Powered by blists - more mailing lists