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Date:   Sat, 23 May 2020 10:19:52 -0700
From:   Andy Lutomirski <luto@...nel.org>
To:     Arvind Sankar <nivedita@...m.mit.edu>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        X86 ML <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: Re: x86: Question about state of general purpose registers on switch
 to 64-bit mode

On Sat, May 23, 2020 at 8:57 AM Arvind Sankar <nivedita@...m.mit.edu> wrote:
>
> Hi,
>
> I have a question about the state of the upper 32 bits of the general
> purpose registers following a switch from/to 64-bit mode.
>
> Both the AMD [0] and Intel [1] manuals state that these bits are
> undefined following a switch from 64 to 32-bit mode. Since they can't be
> accessed in 32-bit mode, presumably this means they are undefined once
> you switch back to 64-bit mode and can see them again.

I would guess that all x86_64 CPUs actually preserve those registers
across mode changes and clear the high bits on 32-bit operations.  But
making the kernel boot code more robust sounds entirely sensible to
me.

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