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Message-ID: <CAHk-=wgkXWbmRmbkOUxZWnh+stxSQjoCsD=E_ZuZr98CAdUgEg@mail.gmail.com>
Date:   Sat, 23 May 2020 10:24:32 -0700
From:   Linus Torvalds <torvalds@...ux-foundation.org>
To:     Arvind Sankar <nivedita@...m.mit.edu>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
        "the arch/x86 maintainers" <x86@...nel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: x86: Question about state of general purpose registers on switch
 to 64-bit mode

On Sat, May 23, 2020 at 8:57 AM Arvind Sankar <nivedita@...m.mit.edu> wrote:
>
> (1) We assume that registers that are set in 32-bit mode will have their
> upper 32 bits clear when we switch to 64-bit mode.

Realistically, I don't think that is what happens.

The upper bits probably won't actually be affected at all by the
switch to 64-bit mode.

But they will be clear in practice, because any 32-bit operation done
in 32-bit mode will _probably_ still be doing the same thing that a
32-bit operation does in 64-bit mode: clearing the upper bits.

> (2) We assume that 64-bit registers that are not touched by the 32-bit
> code will retain their full 64-bit values on switching back.

Again, I think that this is the same as the switch the other way:
switching modes does absolutely nothing to the upper bits.

> Given that we don't keep seeing random boot failures, I would guess that
> the above assumptions are actually valid in practice. However, they do
> seem to be more than what the processors actually promise.

I think you're right. It's not an architectural guarantee, just a
"this is how it happens to work" behavior.

                  Linus

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