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Date: Sun, 24 May 2020 23:12:57 -0500 From: Samuel Holland <samuel@...lland.org> To: Thomas Gleixner <tglx@...utronix.de>, Jason Cooper <jason@...edaemon.net>, Marc Zyngier <maz@...nel.org>, Rob Herring <robh+dt@...nel.org>, Maxime Ripard <mripard@...nel.org>, Chen-Yu Tsai <wens@...e.org>, Russell King <linux@...linux.org.uk>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org> Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com, Samuel Holland <samuel@...lland.org> Subject: [PATCH v2 4/9] ARM: dts: sunxi: h3/h5: Add r_intc node The H3 and H5 SoCs have an additional interrupt controller in the RTC power domain that can be used to enable wakeup for certain IRQs. Add a node for it. Signed-off-by: Samuel Holland <samuel@...lland.org> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 01a5df9aa71b..94f648ad1c9e 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -836,6 +836,15 @@ rtc: rtc@...0000 { #clock-cells = <1>; }; + r_intc: interrupt-controller@...0c00 { + compatible = "allwinner,sun8i-h3-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c00 0x400>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + r_ccu: clock@...1400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>; -- 2.24.1
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