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Date: Sun, 24 May 2020 23:12:58 -0500 From: Samuel Holland <samuel@...lland.org> To: Thomas Gleixner <tglx@...utronix.de>, Jason Cooper <jason@...edaemon.net>, Marc Zyngier <maz@...nel.org>, Rob Herring <robh+dt@...nel.org>, Maxime Ripard <mripard@...nel.org>, Chen-Yu Tsai <wens@...e.org>, Russell King <linux@...linux.org.uk>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org> Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com, Samuel Holland <samuel@...lland.org> Subject: [PATCH v2 5/9] ARM: dts: sunxi: h3/h5: Move wakeup-capable IRQs to r_intc All IRQs that can be used to wake up the system must be routed through r_intc, so they are visible to firmware while the system is suspended. For the H3/H5, r_intc IRQ numbers are offset by 32 from the GIC IRQ numbers. Signed-off-by: Samuel Holland <samuel@...lland.org> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 94f648ad1c9e..93e7ce60a64b 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -829,8 +829,9 @@ hdmi_phy: hdmi-phy@...0000 { rtc: rtc@...0000 { /* compatible is in per SoC .dtsi file */ reg = <0x01f00000 0x400>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&r_intc>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out", "iosc"; clocks = <&osc32k>; #clock-cells = <1>; @@ -865,7 +866,8 @@ ir: ir@...2000 { clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; resets = <&r_ccu RST_APB0_IR>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&r_intc>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01f02000 0x400>; status = "disabled"; }; @@ -886,7 +888,8 @@ r_i2c: i2c@...2400 { r_pio: pinctrl@...2c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&r_intc>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; -- 2.24.1
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