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Message-ID: <159054633712.88029.2188316950952149370@swboyd.mtv.corp.google.com>
Date: Tue, 26 May 2020 19:25:37 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Sivaprakash Murugesan <sivaprak@...eaurora.org>, agross@...nel.org,
bjorn.andersson@...aro.org, devicetree@...r.kernel.org,
jassisinghbrar@...il.com, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
mturquette@...libre.com, robh+dt@...nel.org
Cc: Sivaprakash Murugesan <sivaprak@...eaurora.org>
Subject: Re: [PATCH V5 0/8] Add APSS clock controller support for IPQ6018
Quoting Sivaprakash Murugesan (2020-05-24 03:04:38)
> The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO,
> these are connected to a clock mux and enable block.
>
> This patch series adds support for these clocks and inturn enables clocks
> required for CPU freq.
What is your intended merge path? You sent this to qcom SoC maintainers,
mailbox maintainers, and clk maintainers. Who is supposed to apply the
series? Should it be split up and taken through various trees? Are there
dependencies? Please add more details to help us.
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