linux-kernel - Re: [PATCH v3 09/10] dmaengine: dw: Introduce max burst length hw config

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Date:   Thu, 28 May 2020 18:40:22 +0300
From:   Serge Semin <Sergey.Semin@...kalelectronics.ru>
To:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
CC:     Serge Semin <fancer.lancer@...il.com>,
        Vinod Koul <vkoul@...nel.org>,
        Viresh Kumar <vireshk@...nel.org>,
        Dan Williams <dan.j.williams@...el.com>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Arnd Bergmann <arnd@...db.de>,
        Rob Herring <robh+dt@...nel.org>, <linux-mips@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <dmaengine@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 09/10] dmaengine: dw: Introduce max burst length hw
 config

On Thu, May 28, 2020 at 05:52:24PM +0300, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 01:50:20AM +0300, Serge Semin wrote:
> > IP core of the DW DMA controller may be synthesized with different
> > max burst length of the transfers per each channel. According to Synopsis
> > having the fixed maximum burst transactions length may provide some
> > performance gain. At the same time setting up the source and destination
> > multi size exceeding the max burst length limitation may cause a serious
> > problems. In our case the DMA transaction just hangs up. In order to fix
> > this lets introduce the max burst length platform config of the DW DMA
> > controller device and don't let the DMA channels configuration code
> > exceed the burst length hardware limitation.
> > 
> > Note the maximum burst length parameter can be detected either in runtime
> > from the DWC parameter registers or from the dedicated DT property.
> > Depending on the IP core configuration the maximum value can vary from
> > channel to channel so by overriding the channel slave max_burst capability
> > we make sure a DMA consumer will get the channel-specific max burst
> > length.
> 
> ...
> 
> >  static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
> >  {
> > +	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
> >  
> 

> Perhaps,
> 
> 	/* DesignWare DMA supports burst value from 0 */
> 	caps->min_burst = 0;

Regarding min_burst being zero. I don't fully understand what it means.
It means no burst or burst with minimum length or what?
In fact DW DMA burst length starts from 1. Remember the burst-length run-time
parameter we were arguing about? Anyway the driver makes sure that both
0 and 1 requested burst length are setup as burst length of 1 in the
CTLx.SRC_MSIZE, CTLx.DST_MSIZE fields.

I agree with the rest of your comments below.

-Sergey

> 
> > +	caps->max_burst = dwc->max_burst;
> >  }
> 
> ...
> 
> > +	*maxburst = clamp(*maxburst, 0U, dwc->max_burst);
> 
> Shouldn't we do the same for iDMA 32-bit? Thus, perhaps do it in the core.c?
> 
> >  	*maxburst = *maxburst > 1 ? fls(*maxburst) - 2 : 0;
> 
> > +	if (!of_property_read_u32_array(np, "snps,max-burst-len", mb,
> > +					nr_channels)) {
> > +		for (tmp = 0; tmp < nr_channels; tmp++)
> > +			pdata->max_burst[tmp] = mb[tmp];
> 
> I think we may read directly to the array. This ugly loops were introduced due
> to type mismatch. (See below)
> 
> > +	} else {
> > +		for (tmp = 0; tmp < nr_channels; tmp++)
> > +			pdata->max_burst[tmp] = DW_DMA_MAX_BURST;
> > +	}
> 
> And this will be effectively memset32().
> 
> >  	unsigned char	nr_masters;
> >  	unsigned char	data_width[DW_DMA_MAX_NR_MASTERS];
> >  	unsigned char	multi_block[DW_DMA_MAX_NR_CHANNELS];
> > +	unsigned int	max_burst[DW_DMA_MAX_NR_CHANNELS];
> 
> I think we have to stop with this kind of types and use directly what is in the
> properties, i.e.
> 
> 	u32 max_burst[...];
> 
> -- 
> With Best Regards,
> Andy Shevchenko
> 
>