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Message-ID: <159072524643.69627.17142536778465322331@swboyd.mtv.corp.google.com>
Date:   Thu, 28 May 2020 21:07:26 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>,
        linux-clk@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, linux-snps-arc@...ts.infradead.org,
        Michael Turquette <mturquette@...libre.com>,
        Alexey Brodkin <Alexey.Brodkin@...opsys.com>,
        Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
Subject: Re: [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing

Quoting Eugeniy Paltsev (2020-03-11 06:41:14)
> Support setting PLL to bypass mode to support output frequency
> equal to input one.
> 
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
> ---

Applied to clk-next

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