linux-kernel - Re: [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first

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Message-ID: <159072524355.69627.3014845775029445369@swboyd.mtv.corp.google.com>
Date:   Thu, 28 May 2020 21:07:23 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>,
        linux-clk@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, linux-snps-arc@...ts.infradead.org,
        Michael Turquette <mturquette@...libre.com>,
        Alexey Brodkin <Alexey.Brodkin@...opsys.com>,
        Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
Subject: Re: [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first

Quoting Eugeniy Paltsev (2020-03-11 06:41:13)
> If PLL is bypassed the EN (enable) bit has no effect on
> output clock.
> 
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
> ---

Applied to clk-next